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Own microarchitecture and synthesizable SystemVerilog RTL for major AI accelerator blocks from specification through tape-out. Drive power, performance, and area optimization, timing closure, synthesis, STA, lint, CDC, LEC, assertions, and verification collaboration. Partner with architecture and software teams on performance improvements, advance EDA automation, lead design reviews, and mentor engineers.

Leads end-to-end design verification for next-generation machine learning ASICs through tape-out and first-silicon bring-up. Owns verification architecture, methodology, coverage, performance validation, emulation, FPGA prototyping, debug, schedules, and tape-out readiness. Manages and grows an experienced team of 8–10 engineers, including principal-level staff, while partnering with architecture, design, software, compiler, runtime, hardware, and systems teams.

Design and implement block- and SoC-level DFT architectures for complex AI accelerator chips. Develop ATPG, MBIST, scan, JTAG, IEEE 1500, and IJTAG infrastructure; automate insertion, pattern generation, coverage analysis, and debug; support DFT timing closure, ATE deployment, silicon bring-up, diagnosis, failure localization, yield analysis, and manufacturing test optimization.

As a Senior Cloud SRE, you'll ensure the reliability and performance of our AI inferencing service, handle incident management, and optimize cloud infrastructure and resource utilization.

Develop and execute verification plans for complex AI chip control and initialization features. Build SystemVerilog and UVM environments, tests, assertions, checkers, and coverage models. Verify sequencing, state transitions, clocking, recovery, and cross-domain interactions. Debug simulation and regression failures, analyze coverage, identify root causes, and drive verification closure while collaborating with architects, RTL designers, firmware engineers, and verification teams.

Own hardware emulation models and platform infrastructure for next-generation AI accelerator chips. Build transactors, behavioral and memory models using SystemVerilog and C/C++, ensure RTL and IP are emulation-ready, and automate continuous regression testing. Lead emulation flows, partitioning, performance tuning, vendor relationships, and platform capacity. Support software bring-up, performance verification, functional regression acceleration, and silicon debug while providing technical leadership across design, verification, and software teams.

Architects RDU-based AI accelerator platforms spanning boards, servers, racks, clusters, interconnect fabrics, power delivery, and thermal systems. Responsibilities include defining specifications, selecting components, evaluating ODM/OEM partners, modeling performance and cost, leading bring-up and qualification, investigating reliability issues, and guiding systems through production and deployment. The role also requires cross-functional technical leadership, executive communication, vendor accountability, and mentoring across hardware, software, performance, and datacenter operations teams.

Design and own RTL hardware blocks for AI accelerator ASICs through microarchitecture, implementation, tapeout, and silicon bring-up. Develop high-performance SystemVerilog designs, meet power, performance, and area targets, and collaborate with verification and physical design teams. Implement assertions and run lint, CDC, LEC, synthesis, and timing flows. Support design reviews, post-silicon debugging, and improvements to ASIC design methodologies, including AI and automation in EDA workflows.

Integrate AI accelerator platforms into prototype and production rack-scale systems for customer datacenter deployment. Configure network, power, and compute equipment; develop scalable, manufacturable, and serviceable rack solutions; collaborate with architects, engineering, datacenter, sales, and marketing teams; and manage vendor partnerships. The role also supports rack design, networking, cooling, power systems, prototyping, and conversion to mass production.

Define and own networking architecture for next-generation super-pod ML hardware. Lead R&D, specify high-performance networking fabrics, drive ML networking roadmap, collaborate cross-functionally across silicon, systems, and software, contribute to industry standards, and deliver performant, reliable, and secure interconnect solutions at scale.