The era of pervasive AI has arrived. In this era, organizations will use generative AI to unlock hidden value in their data, accelerate processes, reduce costs, drive efficiency and innovation to fundamentally transform their businesses and operations at scale.
SambaNova Suite™ is the first full-stack, generative AI platform, from chip to model, optimized for enterprise and government organizations. Powered by the intelligent SN40L chip, the SambaNova Suite is a fully integrated platform, delivered on-premises or in the cloud, combined with state-of-the-art open-source models that can be easily and securely fine-tuned using customer data for greater accuracy. Once adapted with customer data, customers retain model ownership in perpetuity, so they can turn generative AI into one of their most valuable assets.
The emulation team builds the pre-silicon model of SambaNova's RDU that the software, architecture, and verification teams depend on.
About the roleSambaNova is looking for a Senior Principal Engineer to build and own the hardware emulation models for our next-generation Reconfigurable Dataflow Unit — the silicon behind our AI workload acceleration systems.
Emulation is a development platform here, not a checkbox. Our software teams bring up drivers, runtime, and compiler against the emulation model months before silicon. Our architects measure performance on it. Our verification team runs on it to get through scenarios that simulation cannot reach in useful time. When the model is fast, accurate, and available, three organizations move faster; when it is not, they wait.
Building that model is the core of the job. You will work shoulder to shoulder with the RTL design team to keep the design emulation-compliant, decide where a vendor model will do and where you need to write a custom one, and own the automation that keeps the platform running tests continuously rather than by hand. This is a senior individual-contributor role, and much of its leverage comes through other teams: you will be the person design, verification, and software engineers consult on what emulation can and should do, and the one who holds our emulator vendors to account.
Responsibilities
Build the models
- Develop the emulation model for each new RDU generation: high-performance transactors, behavioral models, and memory models in SystemVerilog and C/C++
- Partner with the RTL design team to keep the design emulation-compliant: review RTL and IP for constructs that will not map cleanly to the emulator, and close the gaps by substituting vendor emulation models or hand-coding custom models where no vendor model exists
- Own model fidelity: make sure substituted and custom models track design intent closely enough that software, performance, and verification results can be trusted
- Influence design decisions upstream so emulation-readiness is designed in rather than worked around
Own the platform, flows, and automation
- Own the emulation environment architecture: build and runtime flows, partitioning, compile strategy, clocking, and memory configuration for each chip generation
- Build and own the workflows that automate emulation testing on the hardware: job scheduling, regression launch, failure triage, and results reporting, so the platform runs continuously without manual babysitting
- Own throughput and capacity: profile and remove bottlenecks in models, transactors, and testbench collateral so turnaround stays fast as the design grows
- Own the emulator vendor relationship: drive blocking tool issues to resolution, hold the vendor accountable to our program schedule, and advise on platform selection and capacity investment
Serve the three primary use cases
- Software and hardware co-development: deliver and sustain the platform software teams depend on for pre-silicon bring-up of drivers, runtime, and compiler, and debug hardware/software integration failures alongside them
- Performance verification: enable workload bring-up, measurement methodology, and reproducible results, and work with architecture to correlate emulated performance against architectural models
- Verification acceleration: partner with design verification to move long-running and full-chip regressions onto emulation reliably, including system-level and gate-level scenarios that are impractical in simulation
- Silicon debug, secondary to the above: reproduce post-silicon issues on emulation when lab debug needs a controllable, fully visible model
Technical Leadership
- Own the emulation methodology and mentor engineers on it, and act as the authority design, verification, and software teams consult when deciding what belongs on emulation
Required Qualifications
- BS or MS in EE, CE, or CS with 10+ years (or equivalent) of industry experience, including deep hands-on emulation work
- Hands-on expertise bringing up and sustaining designs on an industry-standard emulation platform such as Palladium, Veloce, or Zebu: compile flows, partitioning, debug capabilities, and performance tuning
- Strong SystemVerilog together with C/C++, applied to building transactors, behavioral models, memory models, and co-emulation infrastructure
- Experience making a design emulation-ready: identifying RTL and IP that will not map to the emulator, and resolving it by substituting vendor emulation models or coding custom models
- Track record owning an emulation platform across at least one full chip program, from bring-up through tape-out, including enabling software teams to run a real stack against the pre-silicon model
- Track record owning an emulator vendor relationship: driving blocking tool issues to resolution and evaluating and landing new platform capabilities
- Experience applying emulation to performance analysis, to accelerating functional verification regressions, or both
- Deep debug ability across the hardware/software boundary: able to localize a failure that could be RTL, model, transactor, flow, or software
- Scripting and automation in Python and shell: building the regression, scheduling, and triage workflows that keep an emulation platform continuously utilized
- Demonstrated technical leadership without formal authority: setting methodology direction across design, verification, and software teams
Preferred Qualifications
- MS or PhD in EE, CE, or CS with 12+ years of experience
- Depth on Cadence Palladium
- Hands-on experience on more than one emulation platform, with judgment about the trade-offs between them
- Machine learning accelerators, dataflow architectures, or reconfigurable silicon
- High-speed interconnect and memory modeling: PCIe, Ethernet, HBM/DDR
- Virtual or hybrid platforms combining emulation with instruction-accurate models
- FPGA prototyping platforms and design partitioning for prototyping
- Post-silicon debug, reproducing lab failures on a pre-silicon platform
- Compiler or runtime software background, or experience embedded on a software team
- Fluency with Claude or other AI tools applied to flow development and automation
Base Salary Range:
Submission Guidelines
Please note that in order to be considered an applicant for any position at SambaNova Systems, you must submit an application form for each position for which you believe you are qualified.
EEO Policy
SambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws.
Benefits Summary for US-Based, Full-Time Employment Positions
SambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well-being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.
Skills Required
- Bachelor’s or master’s degree in electrical engineering, computer engineering, or computer science, or equivalent industry experience
- 10 or more years of industry experience, including deep hands-on hardware emulation experience
- Hands-on experience with an industry-standard emulation platform such as Palladium, Veloce, or ZeBu
- Expertise with emulation compile flows, partitioning, debug capabilities, and performance tuning
- Strong SystemVerilog and C/C++ skills for transactors, behavioral models, memory models, and co-emulation infrastructure
- Experience making RTL and IP designs emulation-ready using vendor or custom emulation models
- Ownership of an emulation platform across at least one complete chip program from bring-up through tape-out
- Experience enabling software teams to run drivers, runtime, and compiler stacks against pre-silicon models
- Experience owning emulator vendor relationships and resolving blocking tool issues
- Experience applying emulation to performance analysis or functional verification acceleration
- Ability to debug across RTL, models, transactors, flows, and software
- Python and shell scripting experience for regression, scheduling, and triage automation
- Demonstrated technical leadership without formal authority
- Master’s or PhD in electrical engineering, computer engineering, or computer science with 12 or more years of experience
- Depth with Cadence Palladium
- Experience with multiple emulation platforms
- Experience with machine learning accelerators, dataflow architectures, or reconfigurable silicon
- High-speed interconnect and memory modeling experience, including PCIe, Ethernet, HBM, or DDR
- Experience with virtual or hybrid platforms combining emulation and instruction-accurate models
- FPGA prototyping and design partitioning experience
- Post-silicon debug and reproducing lab failures on pre-silicon platforms
- Compiler or runtime software background, or experience embedded on a software team
- Fluency with Claude or other AI tools applied to flow development and automation
What We Do
AI is changing the world and at SambaNova, we believe that you don’t need unlimited resources to take advantage of the most advanced, valuable AI capabilities - capabilities that are helping organizations explore the universe, find cures for cancer, and giving companies access to insights that provide a competitive edge. We deliver the world’s fastest and only complete AI solution for enterprises and governments with world-record inference performance and accuracy. Powered by the SambaNova SN40L Reconfigurable Dataflow Unit (RDU), organizations can build a technology backbone for the next decade of AI innovation with SambaNova Suite. Our fully integrated hardware-software system, DataScale®, enables organizations to train, fine-tune, and deploy the most demanding AI workloads using the largest and most challenging models. Most recently, with the launch of our newest offering, SambaNova Cloud, developers can supercharge AI-powered applications on Llama 3.2 models. SambaNova was founded in 2017 in Palo Alto, California, by a group of industry luminaries, business leaders, and world-class innovators who understand AI. Today, we’ve built an incredibly smart and motivated team dedicated to making a lasting impact on the industry and equipping our customers to thrive in the new era of AI.
Why Work With Us
As a talent first company, we aim to hire the greatest and most innovative minds in the industry- driving the next generation of AI computing where no barrier is too high and the possibilities are truly limitless. We encourage our peers to take risks and take the initiative to make a lasting impact on the AI and ML industries.
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