AI Hardware System Architect

The System Architecture team owns architecture for RDU-based platforms at the board, rack, and cluster level, covering SambaRack-class server and rack design, the scale-up and scale-out interconnect fabric, power delivery, and air and liquid cooling. We write the specifications ODM/OEM and component partners build to, evaluate their proposals, and make the build, buy, and co-develop calls. We define the bring-up, validation, and qualification plan for each platform, and work with signal and power integrity engineers, SambaFlow, ML performance, and datacenter operations to keep architecture decisions matched to the workloads running on the systems.

SambaNova's Reconfigurable Dataflow Unit (RDU) powers a full-stack, chip-to-model AI platform used by enterprise and government customers, delivered both on-premises and in the cloud. As a Senior RDU System Architect, you'll be a part of the team that turns silicon into shippable systems — SambaRack-class server and rack designs, the scale-up/scale-out fabric that links RDUs together, and the power and cooling envelope that lets dense AI compute run efficiently in a real data hall. You'll set direction across build, buy, and co-design decisions with our hardware partners, write the specifications those partners build to, and stay engaged from architecture definition through bring-up, qualification, and fleet deployment.

Platform & Rack Architecture

• Being a part of the team defining the architecture of RDU-based server and rack platforms, from board layout and chassis design through full-rack integration, translating product and customer requirements into system specifications that engineering teams and vendors can build to.
• Select and validate major system components — RDU sockets, memory modules, power supplies, chassis mechanicals — balancing performance, power envelope, and manufacturability.
• Build performance and cost models to compare candidate rack configurations before committing to a design.

Fabric, Power & Thermal

• Architect the scale-up and scale-out interconnect fabric that links RDUs into larger training and inference clusters, choosing topology, switch/NIC hardware, and optics to hit bandwidth and latency targets.
• Own the power delivery architecture (including high-density/48V-class distribution) and the cooling strategy — air and liquid — needed to keep dense, multi-socket racks within thermal budget.
• Work with signal and power integrity engineers to confirm interconnect and power designs hold up once they leave simulation and reach the lab.

Partner & Supply Chain Engineering

• Evaluate ODM/OEM and component vendor proposals against SambaNova's system requirements, and decide where to build in-house, buy off the shelf, or co-develop with a partner.
• Flag schedule or technical risk in partner designs early, and drive the changes needed to close the gap.
• Maintain a working map of the vendor and technology landscape — boards, interconnect, power, cooling — that feeds SambaNova's platform roadmap.

Bring-Up, Qualification & Field Reliability

• Define the bring-up, validation, and qualification plan for each new platform, including the reliability (RAS) and telemetry targets it needs to hit once it's running in a customer's data hall.
• Lead root-cause investigations when a platform's measured behavior in the lab or field diverges from the architecture's projections.

Cross-Team Technical Leadership

• Partner with the SambaFlow software/compiler team, ML performance, and datacenter operations so system architecture choices actually help the workloads running on top of them.
• Brief executive leadership on architecture tradeoffs and keep the roadmap aligned to customer and product priorities.
• Mentor engineers on system architecture methodology, and help build the review process and spec standards the team uses going forward.

• B.S. or M.S. in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience
• 12+ years architecting hardware systems for hyperscale, HPC, or AI/ML infrastructure
• Deep, hands-on background in at least one systems domain, such as interconnect, power delivery, thermal/cooling, or mechanical, for large-scale AI accelerator, HPC, or hyperscale systems
• Experience owning system architecture at board, rack, or cluster scale, including writing the specs that other engineering teams and vendors build to
• A track record of carrying a system through architecture definition, bring-up, and volume production
• Direct experience holding external vendors and ODM/OEM partners accountable to a technical specification
• Comfortable reasoning across domains that affect each other, for example how an interconnect choice changes the power and thermal budget, which in turn changes the mechanical design
• A history of making and owning directional calls, and building alignment across engineering and partner teams to support them
• Clear technical writing, specs and reviews other teams will build to and rely on

• Hands-on experience with AI accelerator platforms (RDU, GPU, TPU, or custom ASIC) and the fabrics that scale them up and out
• Enough fluency in chip- and package-level design to work as a peer with silicon and packaging architects, even though that is not this role's primary scope
• Experience standing up a new engineering function, review process, or design practice from scratch