Design Verification Engineer

Posted 3 Days Ago
Be an Early Applicant
San Jose, CA, USA
In-Office
120K-200K Annually
Senior level
Artificial Intelligence • Hardware • Machine Learning • Natural Language Processing • Software • Generative AI
SambaNova is the #1 platform for business AI.
The Role
Develop and execute verification plans for complex AI chip control and initialization features. Build SystemVerilog and UVM environments, tests, assertions, checkers, and coverage models. Verify sequencing, state transitions, clocking, recovery, and cross-domain interactions. Debug simulation and regression failures, analyze coverage, identify root causes, and drive verification closure while collaborating with architects, RTL designers, firmware engineers, and verification teams.
Summary Generated by Built In

The era of pervasive AI has arrived. In this era, organizations will use generative AI to unlock hidden value in their data, accelerate processes, reduce costs, drive efficiency and innovation to fundamentally transform their businesses and operations at scale.

SambaNova Suite™ is the first full-stack, generative AI platform, from chip to model, optimized for enterprise and government organizations. Powered by the intelligent SN40L chip, the SambaNova Suite is a fully integrated platform, delivered on-premises or in the cloud, combined with state-of-the-art open-source models that can be easily and securely fine-tuned using customer data for greater accuracy. Once adapted with customer data, customers retain model ownership in perpetuity, so they can turn generative AI into one of their most valuable assets.

About the team

The Design Verification team works on the RDU, SambaNova's chip for machine learning and AI workloads. This group focuses on chip-level control and initialization: sequencing, state transitions, clocking, and recovery across multiple subsystems on the chip. You'll build SystemVerilog and UVM verification environments alongside architects, RTL designers, and firmware engineers, and take ownership of verification plans from first draft through closure. The team works closely with the broader verification organization, so debugging and root-causing issues often means coordinating across groups rather than working in isolation.

About the role

SambaNova Systems is looking for a talented and motivated Design Verification Engineer, DFT to help us build state of the art RDU chips for machine learning and artificial intelligence.

Responsibilities

Some of your responsibilities will include:

  • Develop and execute comprehensive verification plans for complex chip-level control and initialization features
  • Develop SystemVerilog/UVM based verification environments, test sequences, checkers, assertions, and functional coverage
  • Verify complex sequencing, dependencies, state transitions, and recovery scenarios across multiple chip subsystems
  • Develop directed and constrained-random tests to identify architectural and implementation corner cases
  • Closely work with architects, RTL designers, firmware, and other verification teams to understand design intent and drive verification closure
  • Debug simulation and regression failures and work with design teams to root-cause and resolve issues
  • Analyze regression failures, functional and code coverage and drive verification to closure
Required Qualifications
  • B.S. in Computer Science, Computer Engineering, or related field
  • 5+ years relevant industry experience
  • Strong understanding of digital design, SoC architecture, and verification methodologies
  • Strong proficiency in SystemVerilog and UVM is required
  • Experience with constrained-random verification, functional coverage, and assertion-based verification
  • Good understanding of chip initialization, control sequencing, clocking, and cross-domain interactions
  • Strong simulation debug and problem-solving skills
  • Proficiency in scripting languages, e.g. Python, Perl, TCL and shell scripting, etc. is required
Preferred Qualifications
  • Familiarity with CDC/RDC concepts and verification methodologies
  • Fluency in Claude / AI tools for verification development and debug
 

Base Salary Range:

Base Pay Range
$120,000$200,000 USD

Submission Guidelines
Please note that in order to be considered an applicant for any position at SambaNova Systems, you must submit an application form for each position for which you believe you are qualified. 

EEO Policy
SambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws.

Benefits Summary for US-Based, Full-Time Employment Positions
SambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well-being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.

Skills Required

  • Bachelor’s degree in Computer Science, Computer Engineering, or a related field
  • 5+ years of relevant industry experience
  • Strong understanding of digital design, SoC architecture, and verification methodologies
  • Strong proficiency in SystemVerilog and UVM
  • Experience with constrained-random verification, functional coverage, and assertion-based verification
  • Understanding of chip initialization, control sequencing, clocking, and cross-domain interactions
  • Strong simulation debugging and problem-solving skills
  • Proficiency in scripting languages such as Python, Perl, Tcl, and shell scripting
  • Familiarity with CDC/RDC concepts and verification methodologies
  • Fluency in Claude or other AI tools for verification development and debugging
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The Company
HQ: Palo Alto, CA
500 Employees
Year Founded: 2017

What We Do

AI is changing the world and at SambaNova, we believe that you don’t need unlimited resources to take advantage of the most advanced, valuable AI capabilities - capabilities that are helping organizations explore the universe, find cures for cancer, and giving companies access to insights that provide a competitive edge. We deliver the world’s fastest and only complete AI solution for enterprises and governments with world-record inference performance and accuracy. Powered by the SambaNova SN40L Reconfigurable Dataflow Unit (RDU), organizations can build a technology backbone for the next decade of AI innovation with SambaNova Suite. Our fully integrated hardware-software system, DataScale®, enables organizations to train, fine-tune, and deploy the most demanding AI workloads using the largest and most challenging models. Most recently, with the launch of our newest offering, SambaNova Cloud, developers can supercharge AI-powered applications on Llama 3.2 models. SambaNova was founded in 2017 in Palo Alto, California, by a group of industry luminaries, business leaders, and world-class innovators who understand AI. Today, we’ve built an incredibly smart and motivated team dedicated to making a lasting impact on the industry and equipping our customers to thrive in the new era of AI.

Why Work With Us

As a talent first company, we aim to hire the greatest and most innovative minds in the industry- driving the next generation of AI computing where no barrier is too high and the possibilities are truly limitless. We encourage our peers to take risks and take the initiative to make a lasting impact on the AI and ML industries.

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