SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value.
The RTL design team builds the compute datapath, on-chip network, and memory subsystems inside SambaNova's RDU AI accelerator. Their work spans microarchitecture through tape-out, including RTL implementation, PPA trade-offs, quality gates like lint, CDC, and LEC, and timing closure with physical design.
SambaNova is looking for a Principal RTL Design Engineer to own the microarchitecture and RTL for our next-generation Reconfigurable Dataflow Unit (RDU), the silicon behind our AI acceleration systems. This is a senior individual contributor role where you'll take a block from microarchitecture specification through RTL, quality closure, and tape-out, owning the power, performance, and area trade-offs along the way. Frequency targets are aggressive, so how you pipeline a datapath and where you spend area to buy timing are essential aspects of the role.
Responsibilities- Own the microarchitecture and RTL for a major block or subsystem of the RDU, from specification through tape-out, including the specs you write for complex blocks in compute, memory, or on-chip network subsystems
- Write, integrate, and debug synthesizable SystemVerilog RTL through the full chip implementation and production lifecycle
- Own PPA for your area, hitting aggressive frequency targets through datapath pipelining, retiming, and microarchitectural restructuring
- Drive timing closure and design quality for your area: synthesis, STA, critical-path iteration, lint, CDC, LEC, and SystemVerilog Assertions capturing design intent
- Partner with design verification to define verification intent and coverage for your block, and support debug of functional and gate-level failures
- Work with architects and software teams to prototype and evaluate features that improve application-level performance
- Drive AI, automation, and new EDA tool methodologies into the design flow
- Set the technical bar in design reviews and mentor design engineers
- B.S. in Electrical Engineering, Computer Engineering, or Computer Science
- 7+ years of industry experience in ASIC RTL design
- Mastery of synthesizable SystemVerilog for high-speed, high-performance ASICs, including SVA to capture design intent
- High-frequency design experience, including datapath pipelining, retiming, critical-path restructuring, and other microarchitectural techniques for hitting aggressive frequency targets
- Deep foundation in computer architecture and digital logic design, including arbitration, flow control, clock domain crossing, and memory structures
- Ownership of a complex block or subsystem from microarchitecture specification through tape-out on at least one production ASIC
- Experience converging power, performance, and area against real physical constraints, including floorplan, congestion, and timing feedback from the physical design team
- Hands-on experience with synthesis and static timing analysis, and with lint, CDC, and LEC quality flows
- Demonstrated technical leadership without formal authority, including setting direction in design reviews, arbitrating microarchitecture decisions, and mentoring engineers
- Scripting in Python for design and flow automation
- M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science
- Depth in one RDU domain: compute and dataflow datapath, on-chip network and interconnect, or memory subsystem
- Industry-standard interconnects and protocols including AXI, PCIe, Ethernet, and HBM or DDR
- AI and ML workload acceleration techniques, and dataflow or reconfigurable architectures
- Formal property checking applied to design intent
- Advanced TSMC nodes and multi-die or chiplet design
- Performance modeling and analysis to support architectural trade-offs
- Fluency with Claude or other AI tools applied to RTL design and flow development
Base Salary Range:
Submission Guidelines
Please note that in order to be considered an applicant for any position at SambaNova Systems, you must submit an application form for each position for which you believe you are qualified.
EEO Policy
SambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws.
Benefits Summary for US-Based, Full-Time Employment Positions
SambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well-being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.
Skills Required
- B.S. in Electrical Engineering, Computer Engineering, or Computer Science
- 7+ years of industry experience in ASIC RTL design
- Mastery of synthesizable SystemVerilog for high-speed, high-performance ASICs, including SVA
- High-frequency design experience with datapath pipelining, retiming, critical-path restructuring, and microarchitectural techniques
- Deep knowledge of computer architecture and digital logic design, including arbitration, flow control, CDC, and memory structures
- Ownership of a complex block or subsystem from microarchitecture specification through tape-out on at least one production ASIC
- Experience converging power, performance, and area against physical constraints, including floorplan, congestion, and timing feedback
- Hands-on experience with synthesis, static timing analysis, lint, CDC, and LEC quality flows
- Technical leadership without formal authority, including design direction, microarchitecture decisions, and mentoring
- Python scripting for design and flow automation
- M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science
- Depth in compute and dataflow datapath, on-chip network and interconnect, or memory subsystem
- Experience with AXI, PCIe, Ethernet, HBM, or DDR
- AI and ML workload acceleration techniques and dataflow or reconfigurable architectures
- Formal property checking applied to design intent
- Experience with advanced TSMC nodes and multi-die or chiplet design
- Performance modeling and analysis for architectural trade-offs
- Fluency with Claude or other AI tools applied to RTL design and flow development
What We Do
AI is changing the world and at SambaNova, we believe that you don’t need unlimited resources to take advantage of the most advanced, valuable AI capabilities - capabilities that are helping organizations explore the universe, find cures for cancer, and giving companies access to insights that provide a competitive edge. We deliver the world’s fastest and only complete AI solution for enterprises and governments with world-record inference performance and accuracy. Powered by the SambaNova SN40L Reconfigurable Dataflow Unit (RDU), organizations can build a technology backbone for the next decade of AI innovation with SambaNova Suite. Our fully integrated hardware-software system, DataScale®, enables organizations to train, fine-tune, and deploy the most demanding AI workloads using the largest and most challenging models. Most recently, with the launch of our newest offering, SambaNova Cloud, developers can supercharge AI-powered applications on Llama 3.2 models. SambaNova was founded in 2017 in Palo Alto, California, by a group of industry luminaries, business leaders, and world-class innovators who understand AI. Today, we’ve built an incredibly smart and motivated team dedicated to making a lasting impact on the industry and equipping our customers to thrive in the new era of AI.
Why Work With Us
As a talent first company, we aim to hire the greatest and most innovative minds in the industry- driving the next generation of AI computing where no barrier is too high and the possibilities are truly limitless. We encourage our peers to take risks and take the initiative to make a lasting impact on the AI and ML industries.
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