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Serve as a technical pre-sales leader, driving cross-functional campaigns that match Cadence digital design and EDA solutions to customer needs. Build relationships with customer engineering and leadership, influence buying decisions, manage complex technical projects, and support multi-million-dollar sales through technical expertise across the RTL-to-GDSII flow and AI/ML optimization methods.

Lead customer technical engagement for Digital/Custom/Analog/RF design flows (Innovus, Virtuoso), drive adoption of advanced layout and AI-driven automation, translate customer needs to R&D, and expand Cadence Custom IC footprint while supporting executive-level discussions and methodology definition.

Provide administrative support to HR leadership: manage complex calendars across time zones, coordinate domestic and international travel, organize events and meetings, prepare expense reports and purchase requisitions, support special projects, and handle confidential communications while building cross-functional relationships.

Develop software solutions, analyze algorithms, collaborate on architecture, code review, and document design. Requires strong C/C++ proficiency and problem-solving skills.

The Principal Product Engineer will develop and drive customer adoption of AI-driven Layout Automation flows, focusing on analog layout expertise and automation technology, while collaborating with customers.

Develop and maintain EDA tools for transistor-level analysis. Enhance architecture for timing analysis and implement machine learning technologies for improved solutions.

The ATE Test Engineering Architect will lead the development of production test solutions for complex SoCs, including test strategy, execution, yield analysis, and mentoring engineers.

Drive development and customer adoption of Analog Design automation flows in Virtuoso, optimizing and enhancing customer design workflows and methodologies.

Serve as a technical evangelist for Cadence analog design tools and agentic workflows. Demonstrate product capabilities to customers, resolve customer issues with application engineers, advocate customer needs to R&D, and help define improved use models and user interfaces to advance analog/RF/mixed-signal circuit design workflows.

The Infrastructure Architect will lead M&A infrastructure integration efforts, ensuring minimal disruption while optimizing systems and networking across merged environments.