Principal EDA Software Engineer (C++, Characterization)

Reposted 23 Days Ago
Be an Early Applicant
San Jose, CA, USA
In-Office
137K-254K Annually
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Develop and maintain EDA tools for transistor-level analysis. Enhance architecture for timing analysis and implement machine learning technologies for improved solutions.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Join our expert R&D team as we create technologies and products that enable static and dynamic transistor-level analysis of the most advanced custom digital and mixed-signal circuits, powering the communication, IoT, and AI markets.
 

Key Responsibilities
  • Enhance and expand existing tools' architecture to cover timing analysis.
  • Create new frameworks for analyzing effects dominant at n5 and below.
  • Leverage machine learning technology to achieve significant improvements in speed, capacity, and usability over existing solutions.
     
Must-Have Qualifications
  • 8+ years of experience in development of EDA tools and expertise in one or more areas: transistor-level timing, power, noise, aging, reliability, and EMIR analysis.
  • Hardcore C++ knowledge, particularly in a Linux environment.
  • Strong proficiency in designing data structures, algorithms, and applying software engineering principles.
  • Industry experience developing and maintaining C++ based applications on Unix or Linux platforms.
     
Requirements
  • Experience with quality and software processes.
  • Proficiency in designing data structures, algorithms, and software engineering principles.
  • Ability to analyze transistor or gate-level schematics.
  • BS degree in Computer Science, Electrical Engineering, or Computer Engineering preferred.
     
Nice-to-Have Skills
  • Experience in development of circuit simulation or library characterization programs.
  • Understanding of SPICE simulation transistor models at a high level.
  • Experience with distributed programming, database design, and cloud APIs for distributed computing.
     
Why Cadence?

At Cadence, you’ll work alongside industry leaders and innovators who are passionate about advancing technology. Your contributions will directly impact the development of cutting-edge tools and solutions for the communication, IoT, and AI industries. We foster a collaborative environment where your expertise and ideas will shape the technology of tomorrow.
 

Apply Today

If you are ready to make a difference and push the boundaries of EDA technology, we encourage you to apply and join Cadence’s world-class R&D team.

The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • 8+ years of experience in development of EDA tools
  • Hardcore C++ Knowledge - Linux
  • Proficiency in designing data structures, algorithms, and software engineering principles
  • Industry experience developing and maintaining C++ based applications on a Unix or Linux environment

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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