ATE Test Engineering Architect

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San Jose, CA, USA
In-Office
179K-332K Annually
Expert/Leader
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
The ATE Test Engineering Architect will lead the development of production test solutions for complex SoCs, including test strategy, execution, yield analysis, and mentoring engineers.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are seeking a ATE Test Engineering Architect to lead development and deployment of production test solutions for our large complex SoCs deployed in our Emulation Products. This role owns ATE test strategy and execution from first silicon bring‑up through qualification and high‑volume manufacturing, working closely with design, DFT, and global manufacturing partners.

This is a hands‑on technical leadership role for engineers passionate about silicon quality, yield, and scalable test solutions.

Job Responsibilities:

  • Lead ATE test development for wafer sort (CP) and final test (FT)
  • Drive first‑silicon bring‑up, debug, and characterization
  • Define test coverage, binning, guard‑banding, and production release criteria
  • Analyze yield and failure data; drive test‑related yield and quality improvements
  • Partner with DFT, design, OSATs, and test houses to ensure manufacturable solutions
  • Support qualification, production ramp, and sustained manufacturing
  • Mentor engineers and act as a technical test leader across product teams

Job Qualifications:

  • BS with a minimum of 12 years of experience OR MS with a minimum of 10 years of experience OR PhD with a minimum of 8 years of experience
  • Strong hands‑on experience with CP/FT test program development
  • Experience with Advantest 93K ATE platform
  • Solid understanding of DFT and silicon debug
  • Proven experience supporting production and working with offshore test partners
  • Strong problem‑solving and cross‑functional communication skills

The annual salary range for California is $178,500 to $331,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • BS with 12 years of experience or MS with 10 years or PhD with 8 years
  • Strong hands-on experience with CP/FT test program development
  • Experience with Advantest 93K ATE platform
  • Solid understanding of DFT and silicon debug
  • Proven experience supporting production and working with offshore test partners
  • Strong problem-solving and cross-functional communication skills
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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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