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Architect, design, bring-up, and sustain emulation-acceleration hardware system platforms. Lead design reviews, set hardware standards, mentor junior engineers, ensure SI/PI and manufacturability, and drive cross-functional development from concept to production.

Lead SoC/ASIC DFT activities including scan insertion, compression scan, LBIST/MBIST, and ATPG pattern generation. Verify and debug ATPG testbenches and failures, work with synthesis/Verilog testbenches, apply JTAG/IEEE standards, and collaborate across architecture, design, and customers to independently deliver DFT solutions using Cadence flows.

Customer-facing senior engineer developing and deploying hardware emulation and FPGA prototyping solutions. Define requirements for high-speed interfaces (PCIe, CXL), create benchmarks, debug across hardware/software boundaries, drive FPGA/firmware acceleration solutions, and present technical findings to customers and internal teams.

Develop and troubleshoot multi-threaded, distributed physical synthesis software for Cadence’s Innovus Implementation System. Collaborate with global R&D teams, product engineers, technical sales, and customers to deliver engineering solutions and workarounds. Apply C/C++ development, data structures, algorithms, Linux, physical synthesis, timing analysis, and scripting expertise to support integrated circuit physical design workflows.

Develop and optimize Cadence Innovus place-and-route software focused on chip timing, power consumption, and timing closure. Design multithreaded and distributed optimization solutions using strong software engineering, data structures, and algorithmic skills. Collaborate with customers and contribute to physical synthesis, timing analysis, and IC physical design tools. Work primarily in C/C++ on Linux, with Tcl and scripting experience preferred.

The Business Systems Analyst will optimize Quote-to-Cash processes, leverage Salesforce solutions and AI tools, and collaborate with various stakeholders for delivery success.

Seeking a Senior Principal C++ Software Engineer to enhance FPGA prototyping products, focusing on timing algorithms and performance improvements.

Develop partitioning and optimization algorithms and new features for the Protium prototyping platform. Collaborate with geographically distributed teams on implementation specs, and work with technical support and customers to troubleshoot implementation and usage issues.

The role involves developing, troubleshooting, and supporting the Genus Synthesis Solution with a focus on logic synthesis and physical design.

Turn channel data into actionable insights to improve partner behavior and forecasting. Analyze pipeline, deal quality, product mix, program ROI, and sales velocity. Deliver decision-ready recommendations, build dashboards, define data needs, and partner cross-functionally with Sales, Programs, and Ops to drive scalable revenue outcomes.