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Responsible for various DFT aspects, including MBIST, scan insertion, yield improvement, ATE pattern development, and silicon debugging.

Develop next generation products focusing on parallel interfaces. Responsibilities include timing signoff, modeling, PCB analysis, and automating sign-off processes.

Design high-speed Serdes products through DSP engineering, focusing on algorithms, system models, and collaboration with analog/digital designers for production validation.

The Staff AI Development Engineer will design agentic workflows, lead fullstack implementation of applications, mentor teams, and optimize AI-driven automation for various business units.

The ASIC Design Engineer leads design implementations, ensuring quality in multiple disciplines including synthesis, floorplanning, and timing closure with minimal supervision.

The ASIC Design Engineer is responsible for leading complex design implementations, ensuring quality through peer reviews, and adapting to technology changes.

The Digital Signal Processing Engineer will design DSP blocks for optical data center products, focusing on SerDes and high-speed data connectivity, utilizing skills in Verilog, Matlab, and high-speed signal processing.

The Staff AI Development Engineer will design agentic AI solutions, implement fullstack applications, mentor teams, and optimize AI workflows and architecture in collaboration with infrastructure teams.

Responsible for front end design and verification of ASIC design blocks, including architecture definition, logic design, synthesis, and verification through simulation and analysis of timing.

Lead DFT programs including specification, implementation, and verification for ASIC products, focusing on various phases of SoC DFT-related activities and customer interactions.