DFT Engineer

Reposted 23 Days Ago
Be an Early Applicant
3 Locations
In-Office
108K-192K Annually
Senior level
Software • Semiconductor • Manufacturing
The Role
Responsible for various DFT aspects, including MBIST, scan insertion, yield improvement, ATE pattern development, and silicon debugging.
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Job Description:

As a member of our team, you will be responsible for various aspects of DFT, including MBIST and scan insertion, ATPG, ATE pattern development, and yield analysis.
Key Responsibilities:
  • Work closely with the ATE engineer on yield improvement and analysis.
  • Develop ATE patterns, manage the hand-off process, and perform silicon debugging.
  • Participate in block and chip-level DFT implementation, developing and executing all related tasks.
  • Work on DFT lint checking, MBIST architecture, logic insertion, and scan insertion using industry-standard tools.
  • Perform ATPG and pattern simulation for both MBIST and scan.
  • Collaborate with the design, verification, and implementation teams during the DFT design phase, and with the ATE and product development teams during silicon bring-up.
  • Engage with various cross-functional team members, with opportunities to enhance our DFT design methodology.
Required Qualifications:
  • BSEE with 8+ years of relevant experience or MSEE with 6+ years of relevant experience.
  • Required experience in silicon bring-up and yield improvement.
  • Solid understanding of DFT techniques.
  • Proven experience in RTL lint checking, scan compression, scan insertion, and the ATPG process.
  • Experience in MBIST architecture and insertion.
  • Experience in analyzing and debugging simulation failures.
  • Solid understanding of digital logic fundamentals.
  • Strong knowledge of the Mentor Tessent/Synopsys DFT and simulation tool suite.
  • Proficiency with Perl or other scripting languages.
  • Strong communication and interpersonal skills.
  • Plus: Experience in STA constraint development in DFT modes

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $108,000 - $192,000. 

 

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Skills Required

  • BSEE with 8+ years of experience or MSEE with 6+ years of experience
  • Experience in silicon bring-up and yield improvement
  • Understanding of DFT techniques
  • Experience in RTL lint checking and scan insertion
  • Experience in MBIST architecture and insertion
  • Experience in analyzing and debugging simulation failures
  • Understanding of digital logic fundamentals
  • Knowledge of Mentor Tessent/Synopsys DFT tools
  • Proficiency with Perl or other scripting languages
  • Experience in STA constraint development in DFT modes

Broadcom Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Broadcom and has not been reviewed or approved by Broadcom.

  • Equity Value & Accessibility Equity is used broadly through RSUs with quarterly or annual vesting, and an ESPP with a discount and look‑back that can add meaningful upside. Company disclosures show ongoing equity grants, including inducement RSUs tied to acquisitions, underscoring equity’s central role in total rewards.
  • Retirement Support A 401(k) plan with a competitive company match and immediate vesting is consistently highlighted, supporting long‑term savings. Tax‑advantaged accounts like HSA/FSA further strengthen the financial wellness toolkit.
  • Pay Growth & Progression Compensation ceilings in technical tracks are described as high, with wide ranges and very strong totals for experienced engineers. Sales compensation is also characterized as competitive, supporting attractive on‑target earnings.

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The Company
HQ: San Jose, CA
38,985 Employees
Year Founded: 1991

What We Do

Broadcom Inc. (NASDAQ: AVGO) is a global technology leader that designs, develops and supplies semiconductor and infrastructure software solutions.

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