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The role involves defining chip-level floorplan architecture for ASICs, optimizing design for performance and area, and collaborating with cross-functional teams on integration.

The role involves developing and supporting design automation software tools for ASIC development, including scripting, debugging, and training engineers.

Oversee design and verification for SerDes development, including architecture design and RTL development. Emphasize timing analysis and constraints development.

Assist in the design, development, and debugging of firmware for Ethernet NIC products. Conduct testing and collaborate with teams for integration.

The Hardware Engineer will evaluate silicon technology, assess foundry offerings, define technology platforms, and ensure design and process alignment.

Develop and optimize Ethernet NIC drivers at the kernel level across multiple OSs. Key tasks include debugging, performance optimization, and hardware interfacing.

Provide high-level administrative support to senior leadership by managing schedules, travel, budgets, and communication across departments while maintaining confidentiality and discretion.

The SDET will design and execute test plans to ensure software quality, implement automated testing solutions, contribute to Agile processes, and assess security vulnerabilities.

The role involves leading technical vision and architecture for distributed systems, mentoring teams, and ensuring high system performance and reliability. Responsibilities include hands-on implementation and resolving complex challenges.

Lead the DFT verification process for HBM, DDR, and SerDes designs, implementing methodologies, analyzing data, and ensuring design reliability through collaborative efforts with various teams.