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Design and integrate digital circuit logic for image sensor and ISP systems, including sensor timing control, data paths, chip architecture, and SoC integration. Collaborate on PPA optimization, physical design, timing closure, DFT, verification, silicon bring-up, debugging, and image quality tuning. Support validation and production readiness while working with analog, digital, algorithm, and application engineering teams.

Designs and integrates digital circuits for image sensors, including sensor timing control and ISP data pipelines. Responsibilities include chip architecture, RTL design, verification, synthesis, timing closure, DFT, full-chip integration, silicon validation, debugging, image tuning, and customer support. The role collaborates with analog, backend, algorithm, and application engineering teams throughout the ASIC development lifecycle.

Designs, simulates, verifies, and refines multi-gigabit PAM4 SerDes IP and analog/mixed-signal receiver blocks, including TI-SAR ADCs, CTLE, DFE, and AFE components. Responsibilities include CDR development, high-speed testing with oscilloscopes and BERT, analog-digital interface verification, layout optimization, clock and synchronization design, and IP documentation. The engineer collaborates with system and test teams on high-speed interfaces, packages, boards, and system clocks for image sensor and bridge chip products.

Designs, simulates, verifies, debugs, and characterizes embedded analog and mixed-signal circuits, including high-speed I/O, SerDes, FIFO, CDR, and PLLs. Collaborates with system and test engineers on interfaces, package and board design, and system clocks for image sensor and bridge products. Performs high-speed testing with oscilloscopes and BERT, supports layout optimization, verifies analog-digital interfaces, and documents IP and design specifications.

Designs and verifies image sensor processing functions, USB/MIPI high-speed interfaces, and full-chip SoC integration. Responsibilities include chip bring-up, validation, debugging, FPGA development, and architecture, register, interface, and design documentation. Requires digital design expertise covering Verilog RTL, simulation, synthesis, static timing analysis, and formal equivalence. Knowledge of low-power design, FPGA/emulation platforms, SoC architecture, and image processing is beneficial.

Lead full-custom analog IC physical design for CMOS image sensors, including column ADC layout, floorplanning, power and clock planning, chip-level routing, parasitic analysis, physical verification, and GDS tape-out. Optimize image sensor performance, area, noise, matching, and power integrity. Develop layout methodologies, automation scripts, design rules, and SVRF files while coordinating top-level implementation resources and schedules.

Owns product engineering from semiconductor tapeout through mass production. Responsibilities include product definition, DFM input, product introduction and ramp-up, yield analysis and corrective actions, characterization, datasheet finalization, and development and release of wafer probe and final test programs. Supports existing products, resolves technical issues with R&D and manufacturing teams, and drives yield improvements for image sensor and ASIC devices.

Designs, simulates, characterizes, and debugs analog mixed-signal integrated circuits, including high-speed I/O, SerDes, PLLs, CDRs, clock trees, serializers, bias circuits, and ESD protection. Performs post-layout signal-integrity analysis, supports circuit layout and floor planning, verifies RTL synchronization blocks, evaluates performance across process, voltage, temperature, noise, and mismatch conditions, and collaborates with system and test engineers on image sensor and bridge-chip products. Documents design reviews, simulation findings, and project lessons learned.

Characterize and optimize CMOS image sensor performance by bringing up new silicon, validating functionality, developing testing methodologies, analyzing pixel-level and analog/digital subsystems, and identifying improvements. Collaborate with design, process, applications, production, and quality teams to resolve system issues, yield and reliability problems, and transition new products into production.

Design and verify analog and mixed-signal circuits for CMOS image sensors, including pixel arrays, amplifiers, ADCs, bias generators, and reference circuits. Perform SPICE, corner, Monte Carlo, temperature, process variation, noise, layout, parasitic extraction, and post-layout simulations. Optimize sensor performance, address crosstalk and interference, document designs, and collaborate with digital, architecture, test, verification, and validation teams.