Sr. Analog Physical Design Engineer

Posted Yesterday
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Santa Clara, CA, USA
In-Office
157K-160K Annually
Senior level
Semiconductor • Manufacturing
The Role
Lead full-custom analog IC physical design for CMOS image sensors, including column ADC layout, floorplanning, power and clock planning, chip-level routing, parasitic analysis, physical verification, and GDS tape-out. Optimize image sensor performance, area, noise, matching, and power integrity. Develop layout methodologies, automation scripts, design rules, and SVRF files while coordinating top-level implementation resources and schedules.
Summary Generated by Built In
Job Title: Sr. Analog Physical Design Engineer
 
Job Duties:
 
  • Work on detailed column ADC circuit design, with a focus on column layout design. Collaborating with other column ADC designers to optimize column ADC’s performance with minimum silicon area.
  • Conduct cross products column ADC layout comparison and IP layout development and maintenance.
  • Perform RCX extraction of column circuit and critical signals parasitic analysis and propose optimized design to improve column ADC performance and image quality.
  • Conduct image sensor pixel array and column ADC supply analysis using Totem or other methodologies, including worst case P2P resistor extraction, and optimize chip floorplan and power routing.
  • Study design rules for new processes and provide physical design guidelines to the design team. Debug and develop Calibre svrf files when needed.
  • Apply SKILL script to improve productivity and design robustness.
  • Responsible for full-custom analog IC layout and physical verification (DRC/ANT/DFM/ERC/LVS) using industry-standard tools like Cadence Virtuoso and Calibre. 
  • Execute top-level layout and coordinate layout resources and schedules for all modules.
  • Perform floor planning and placements including pad locations, power/clock domain planning, ESD, integration of AMS and digital blocks, and chip-level routing strategy.
  • Lead top-level implementation from floorplan through GDS tape-out. 
  • Develop and maintain layout methodologies and documentation to ensure efficient and consistent design practices. 
 
Requirements:
 
Require Master’s degree or foreign equivalent degree in Electrical Engineering, Electronics Engineering, or a closely related field.
 
Require 2 years of experience in CMOS image sensor IC layout design.
 
Require the following experience or skills:
  • Semiconductor process and device fundamentals, with expertise in addressing advanced technology nodes challenges.
  • Experience in image sensor manufacturing technology, performance metrics, and system-level integration in camera applications. 
  • Experience with industry standard EDA tools, such as Cadence Virtuoso, PVS, Spectre, Innovus, Skipper, Siemens Calibre, Synopsys Hspice, Design Compiler, IC Compiler, PrimeTime, Laker and P2P. 
  • Front-end and back-end ASIC design flows.
  • Experience in stacked chip process flow and related design considerations.
  • Skills in interpreting physical verification reports (DRC, DFM, ERC, LVS, etc.) and understanding SVRF rule files.
  • Advanced layout skills such as common-centroid layouts, symmetrical layouts, use of dummy devices, matching, ESD, latch-up, antenna effects, etc.
  • Understanding of layout impact on device matching, noise coupling, guard-ring, electromigration, isolation and IR drop.
  • Developing CAD flow automation using scripting languages like Perl, Skill, and Tcl.
  • Expertise in low-power, high-precision, high speed analog layout design techniques.
  • Solving crosstalk challenges between adjacent column ADCs in image sensor circuits.
 
Annual base salary for this role in California, US is expected to be between $156,853 - $160,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.
 

Skills Required

  • Master's degree or foreign equivalent in Electrical Engineering, Electronics Engineering, or a closely related field
  • At least 2 years of experience in CMOS image sensor IC layout design
  • Knowledge of semiconductor process and device fundamentals, including advanced technology node challenges
  • Experience with image sensor manufacturing technology, performance metrics, and camera system-level integration
  • Experience with industry-standard EDA tools, including Cadence Virtuoso, PVS, Spectre, Innovus, Skipper, Siemens Calibre, Synopsys HSPICE, Design Compiler, IC Compiler, PrimeTime, Laker, and P2P
  • Experience with front-end and back-end ASIC design flows
  • Experience with stacked chip process flows and related design considerations
  • Ability to interpret DRC, DFM, ERC, LVS, and other physical verification reports
  • Understanding of SVRF rule files
  • Advanced analog layout skills, including common-centroid and symmetrical layouts, dummy devices, matching, ESD, latch-up, and antenna effects
  • Understanding of device matching, noise coupling, guard rings, electromigration, isolation, and IR drop
  • Ability to develop CAD flow automation using Perl, SKILL, and Tcl
  • Expertise in low-power, high-precision, and high-speed analog layout design techniques
  • Experience solving crosstalk challenges between adjacent column ADCs in image sensor circuits
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The Company
HQ: Santa Clara, California
1,448 Employees
Year Founded: 1985

What We Do

Founded in 1995, OMNIVISION has been at the leading-edge of technology, developing and delivering advanced digital imaging, analog, and touch & display solutions for multiple applications across several industries. With more than 3,000 employees worldwide and over 13 billion products shipped, OMNIVISION is a well-known global fabless semiconductor company. Our products can be found everywhere in people’s lives including mobile phones, security & surveillance, automotive, computing, medical, and emerging applications. Across these segments, OMNIVISION’S award-winning technology enables a smoother human/machine interface in many of today’s commercial devices. In this way, OMNIVISION delivers solutions that put its customers at the leading edge of technology. Whether it be developing the first mobile handset camera accessory in 2002, introducing the world’s smallest NTS camera in 2006 or launching PureCel CMOS image sensors in 2013, our dedication to providing reliable, innovative imaging and sensing solutions continue to be the primary aim. The company has recorded numerous industry firsts in its relentless quest for technology breakthroughs that deliver #InfiniteIngenuity: • Guinness World Record for the World's Smallest Commercially Available Image Sensor (OV6948) in 2019. In 2021, it beat its own record with the new OH0TA OVMed® • First to commercialize backside illumination technology in 2007 (OmniBSI™) • Industry's 1st to deploy the most mature LED Flicker Mitigation (LFM) solution in mass production for multiple automotive applications • Automotive industry leader with HALE, our HDR & LFM Engine combination algorithm • Developer of Nyxel® near-infrared technology with by far the best quantum efficiency in CMOS near-infrared imagine • Creator of CameraCubeChip™, the industry’s 1st wafer-level camera modules • First and only global shutter image sensors with cybersecurity, for ADAS and autonomous vehicles • First to introduce RBG-Ir technology to medical

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