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Manage a portfolio of Bay Area strategic accounts to drive multi-million-dollar bookings. Build C-level relationships, develop multi-year account strategies, lead complex, multi-stakeholder sales cycles, coordinate cross-functional teams, and expand revenue across Cadence software, hardware, IP, verification, system design and AI-driven solutions.

Design, develop, troubleshoot, and debug R&D software for IC physical design (P&R) as part of the Innovus Implementation System team. Collaborate with global R&D, product engineers, and technical sales to provide engineering solutions and customer support.

Lead and manage M&A and strategic investment transactions end-to-end, provide strategic legal advice to senior management, oversee due diligence, negotiate complex agreements, manage post-investment matters and external counsel, ensure regulatory compliance, and develop playbooks and integration processes.

Lead Cadence's government affairs strategy on exports, national security, AI, U.S.-China relations and industrial policy. Translate policy developments into business risk and actionable insights, engage senior government officials and Congress, manage external lobbying firms and trade associations, coordinate cross-functional teams, represent the company to regulators and policymakers, and produce briefings and recommendations for senior leadership.

Develop performance models, perform architectural tradeoff analysis, and enable data-driven design decisions for DDR memory controller architectures.

The Principal Product Engineer will lead technical evaluations, manage customer projects, provide expertise, and collaborate with sales and engineering teams to enhance product offerings.

The Sr Application Engineer at Cadence is responsible for leading innovative projects that have significant impacts on technology development and problem-solving.

The Product Marketing Manager will lead product strategy and go-to-market execution for Tensilica IP, focusing on customer engagement, market opportunities, and future product requirements.

The Principal Design Engineer will design high-speed analog and mixed-signal circuits, lead design reviews, and collaborate across teams on HBM PHY products.

Lead analog/mixed-signal IC design for high-speed D2D and SERDES products from concept through verification. Collaborate with layout engineers and global teams on circuit blocks (drivers, receivers, PLLs, phase interpolators, bias/bandgap, regulators) using CAD simulation, layout, and physical verification tools. Support architecture and silicon evaluation.