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Managing a SerDes DV group focusing on MDV verification, customer interactions, technical alignment, and developing new verification methodologies. Strong background in functional verification fundamentals and experience in serial bus multiprotocol PHY IPs like PCIe. Expertise in Verilog, SV, e with UVM/OVM/eRM methodology, assertions development, RTL, GLS sim debug, and more. Desirable skills include power-aware RTL set-up, formal verification, gate-level simulations, and exposure to Analog modelling and Automotive IP verification.

The Senior RTL Design Architect at Cadence will be responsible for CPU and interface IP selection, digital design, creating detailed micro-architecture specifications, and collaborating with verification teams. The role emphasizes RTL development and physical design deliverables, ensuring timely IP delivery while working with multidisciplinary teams.

Cadence Design Systems is looking for a highly motivated Principal Software Engineer to join a core team working on Cadence Palladium/Protium product line. Responsibilities include designing and developing start-of-the-art software programs, evaluating complex problems, producing clear design specifications, and working independently to scale solutions for next-generation designs.