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The Design Engineer II will perform post-silicon physical layer electrical validation, manage teams, and lead validation efforts for high-speed SERDES protocols.

Lead the development and management of AI infrastructure, ensuring optimal performance of systems and providing mentorship to engineers while deploying advanced AI models.

Engineer will leverage AI for pre-silicon verification, collaborate with teams, develop AI solutions, and engage customers regarding verification strategies.

Design and implement features for a software analysis tool, troubleshoot software issues, and maintain existing functionalities.

Lead technical sales and evaluation of Cadence SoC verification, simulation, emulation and acceleration solutions. Plan and execute benchmarks, train and support customer projects, deliver demos and advanced trainings, and coordinate product direction with engineering and sales teams while addressing complex technical customer queries.

Work in Cadence's Shanghai Digital & Signoff PE team focusing on backend RC extraction, performance optimization, and final STA signoff. Support key customer engagements and local AEs, act as domain expert to gather customer feedback, and collaborate with R&D to improve tools based on customer demands. Provide backend flow expertise; ECO closure and multi-die design experience are a plus.

Build production-grade AI-driven verification and developer tooling for AVIP: design core software (C++/Rust/Python), implement LLM fine-tuning and prompt engineering, develop multi-agent orchestration, optimize performance-critical components (modern C++, GPU), and maintain tests, validation flows, and cross-team collaboration with verification and AI engineers.

The job involves RTL design for Interface Controller IP, focusing on PCIe Architecture, including subsystem design, feature addition, and customer support.

The Lead Design Engineer will focus on ASIC design and verification, specifically in PCIe and storage technologies, requiring good debug and communication skills.

The Frontend Engineer will support digital IC design implementation, focusing on RTL-to-GDSII methodology and low power design issues, requiring a solid background in IC design and relevant tools.