Design Engineer II

Reposted 9 Days Ago
Be an Early Applicant
Bangalore, Bengaluru Urban, Karnataka, IND
In-Office
Mid level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
The Design Engineer II will perform post-silicon physical layer electrical validation, manage teams, and lead validation efforts for high-speed SERDES protocols.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Minimum Qualifications:

2-4 years (with Btech) or 1-2 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation

Deep Physical Layer electrical validation experience on AT LEAST ONE High speed SERDES protocol like PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO etc

Strong hands on Experience in using lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT) etc

Preferred Qualifications:

Experience managing small teams (at least 2 members and above)

Experience leading the complete post silicon validation efforts for at least one full project

1-2 years of experience in FPGA Design, PCB schematic and layout design & Prototyping

Pre-Silicon IP/SoC Physical Layer Electrical Validation experience related to board bring-up & Debug.

Familiarity with Verilog RTL coding, FPGA coding, Labview, python, C/C++, TCL

Experience conducting hiring interviews and mentoring new hires

BE/BTech/ME/MTech or equivalent

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • 2-4 years of experience in Post-Silicon Physical Layer Electrical Validation with Btech
  • Deep Physical Layer electrical validation experience on at least one High speed SERDES protocol
  • Strong hands on experience in using lab equipment like Oscilloscopes, Network Analyzer, BERT
  • 1-2 years of experience in FPGA Design, PCB schematic and layout design & Prototyping
  • Familiarity with Verilog RTL coding, FPGA coding, Labview, python, C/C++, TCL

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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