Sr Design Engineering Architect

Reposted 11 Days Ago
Be an Early Applicant
Bangalore, Bengaluru Urban, Karnataka, IND
In-Office
6-16 Annually
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
The job involves RTL design for Interface Controller IP, focusing on PCIe Architecture, including subsystem design, feature addition, and customer support.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Description:

  • RTL Design Engineer for Interface Controller IP development team.
  • Position is based in Bangalore or Noida.
  • The role is for PCIe Architect with ARM CPU subsystem architecture, including memory subsystem design, IO and cache subsystems.
  • The role would also include design and support of the RTL of the PCIe/CXL/IDE/UALink IP solution of Cadence.
  • The work involved will be addition of new features into the RTL, working with existing RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring design is clean for LINT and CDC design guidelines.

Position Requirements:

  • BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.
  • 6-16 years of core RTL Design experience using Verilog is a must.
  • System Verilog experience and experience with UVM based environment usage / debugging is required.
  • Architecture and design of CPU subsystem, including memory subsystem design, IO and cache subsystems is a must.
  • PCIe/CXL/IDE experience is highly desirable. Prior experience in implementation of complex protocols is desirable.
  • Prior experience in IP development teams would be an added advantage. 
  • Scripting knowledge is an advantage.
We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • 6-16 years of core RTL Design experience using Verilog
  • Experience with System Verilog and UVM based environment usage/debugging
  • Architecture and design of CPU subsystem
  • PCIe/CXL/IDE experience
  • Prior experience in IP development teams
  • Scripting knowledge

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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