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The Foundry Virtuoso Engineer provides technical support for Virtuoso-based flows, assists with PDK enablement, collaborates with foundry teams on techfiles, and communicates customer issues to product engineers.

Provide technical support for Virtuoso analog backend flows, assist in PDK enablement, and help foundry teams with technology files and QA flow.

The Lead Product Engineer will develop and maintain digital implementation flows, support design service teams, and provide methodology guidance for production SoC designs.

The Principal Product Engineer will develop and drive customer adoption of AI-driven Layout Automation flows, focusing on analog layout expertise and automation technology, while collaborating with customers.

The role focuses on supporting Foundry PDK teams and Design Service teams by enabling EM/IR and thermal signoff technologies, including techfile development and reference flow creation through collaboration and validation of modeling assumptions.

The ATE Test Engineering Architect will lead the development of production test solutions for complex SoCs, including test strategy, execution, yield analysis, and mentoring engineers.

Develop and maintain EDA tools for transistor-level analysis. Enhance architecture for timing analysis and implement machine learning technologies for improved solutions.

The Pegasus Application Engineer supports customer integration and deployment of the Cadence Pegasus Verification System, focusing on physical verification and signoff processes.

The role involves RTL design and support for DDR Memory Controller IP, including design updates, customer support, and adherence to design guidelines.

Drive development and customer adoption of Analog Design automation flows in Virtuoso, optimizing and enhancing customer design workflows and methodologies.