Top Tech Jobs & Startup Jobs

Supports the Lead Paralegal and Japan Legal Department with legal filing, document management, invoice processing, billing reconciliation, and tracking outside counsel payments. Reviews Anti-Corruption approval requests for completeness, follows up on pending items, and provides administrative assistance to attorneys and paralegals. The role also handles confidential information, special projects, and coordination with Finance and Accounts Payable.

Assist with regression reviews for Cadence Innovus place-and-route tools. Develop and maintain system infrastructure to improve productivity and efficiency using scripting and system development techniques. The internship requires at least four days per week for more than six months and involves digital backend flow, IC design, Unix systems, and scripting.

On-site electrical engineering intern validating system-level and electrical performance of silicon test chips. Responsibilities include debugging silicon issues with analog and digital design teams, performing characterization and test automation, preparing reports, and supporting reliable product deployment. Requires strong fundamentals in analog and digital electronics, RTL, signal integrity, and control systems, plus analytical, communication, and teamwork skills.

Drive Cadence digital and signoff product support by applying RTL-to-GDSII, place-and-route, timing closure, and PPA optimization expertise. Collaborate with R&D, applications engineering, marketing, and release teams to resolve customer issues, conduct design benchmarks, and develop customer-specific flows and methodologies. Provide technical guidance on VLSI physical design, clock tree synthesis, routing, timing analysis, and silicon signoff at 7nm and below.

Leads analog and mixed-signal custom layout design for high-speed SERDES and UCIe products, including floor planning, detailed layout, verification, PHY top-level integration, and signoff. Collaborates with circuit designers, project managers, global layout teams, and Cadence R&D. Designs blocks such as drivers, receivers, serializers, PLLs, clock distribution, regulators, and bias circuits while providing technical leadership and maintaining quality and schedule.

Verify digital RTL and develop reusable verification components and environments for high-performance physical IP. Responsibilities include verification flow development, test planning and execution, functional and code coverage closure, assertions, stimulus generation, and collaboration with digital, analog, physical design, project management, and global engineering teams.

Develop and integrate synthesizable SystemVerilog RTL for advanced SoCs and silicon platforms. Translate architecture into microarchitectures, optimize performance, power, and area, and support simulation, verification, synthesis, timing, lint, CDC, IP integration, and downstream implementation. Collaborate with architects, verification, physical design, customers, and multidisciplinary engineering teams while documenting designs and improving RTL methodologies and flows.

The role involves maintaining Unix systems, automating operations, troubleshooting issues, and improving IT infrastructure performance globally within a large team.

Develop and maintain C++ and Tcl algorithms for clock-tree synthesis in Cadence’s Innovus place-and-route tool. Responsibilities include improving scalability, runtime, and memory usage; debugging customer issues; fixing bugs; creating unit tests; running regressions; and validating algorithmic developments on industrial test cases in a global development environment.

Develops, validates, and supports firmware and diagnostic software for complex hardware systems. Responsibilities include hardware bring-up, system validation, manufacturing and field diagnostics, issue triage, low-level debugging, and collaboration with firmware, hardware, validation, product engineering, and field support teams. The role also involves interpreting schematics and specifications, using laboratory debug tools, documenting technical findings, and supporting automated testing and release qualification.