This is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols. The successful candidate will be a highly motivated self-starter who is able to work independently and collaboratively to complete tasks within required project timelines with high quality. The candidate will contribute to digital architecture, digital RTL, low power design, synthesis and timing analysis, and behavioral coding for all IPs in the SerDes physical IP portfolio as well as executing various tool flows for IP quality control. The candidate will be able to work as part of a small and focused team of engineers and will be able to collaborate successfully as needed with design architects, digital verification, project management, and digital and analog design teams in multiple worldwide geographies.
This includes but is not limited to:
- Digital architecture that has an understanding of the trade-offs for power, performance, and area
- Drive architecture to micro-architecture to RTL implementation with the refining of features/requirements throughout the design process
- Understanding of synthesis, constraint generation, power management and DFT
- Understanding of low-power designs and features (power islands, state retention, isolation)
- Work with verification team to specify coverage points, testing strategy, corner conditions and stimulus creation
- Familiarity with uC Based subsystems and their architecture
- Familiarity with AI assisted design practices
Qualifications
- 18-20 years of experience in working with Digital Design and Architecture.
- Must have good written and verbal cross-functional communication skills.
- Proven experience in most of the following:
- Design Architecture
- Design implementation
- Embedded uC Designs
- Synthesis and SDC Creation
- Scripting of design automation
- Debugging verification test cases / SVA’s to cover the design
- Knowledge of existing Serial standards such as PCIE, USB, Ethernet, etc.
- Must be comfortable interacting across the SSG development team including the ability to work with Mixed-signal, Verification and Analog teams
- Should be open to work with AI assisted design practices. Knowledge of AI assisted design flow is plus.
- Knowledge of multiple programming languages. System Verilog, Python, C/C++, etc, are a plus
- Working knowledge of revision control tools such as Perforce, Git, SVN is a plus
- Educational qualifications - minimum Bachelor’s degree, Master’s preferred
Skills Required
- 18-20 years of experience in Digital Design and Architecture
- Design architecture and micro-architecture to RTL implementation
- Design implementation experience (digital RTL, behavioral coding)
- Experience with embedded uC designs and uC-based subsystem architecture
- Synthesis and SDC creation (constraint generation)
- Scripting of design automation
- Debugging verification test cases and SVA assertions
- Knowledge of serial standards (PCIe, USB, Ethernet)
- Understanding of low-power design techniques (power islands, state retention, isolation)
- Familiarity with AI-assisted design practices
- Good written and verbal cross-functional communication skills
- Bachelor's degree (minimum); Master's preferred
- Knowledge of System Verilog, Python, C/C++
- Working knowledge of Perforce, Git, SVN
- Knowledge of AI-assisted design flow
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
Cadence Design Systems Insights
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
