Analog Mixed-Signal Lead Design Engineer (T3) – SerDes
Position Summary
We are seeking an Analog Mixed-Signal Lead Design Engineer (T3) to develop high-speed, low-power SerDes transceivers for data-center, networking, AI, and high-performance computing applications. The engineer will translate system requirements into silicon-ready circuit architectures and collaborate with the architecture, digital, layout, verification, signal integrity, and post-silicon teams.
Key Responsibilities
Design and verify high-speed SerDes blocks, including TX drivers, serializers, RX front ends, CTLEs, samplers, comparators, ADCs, DACs, PLLs, DLLs, clock dividers and distribution networks, regulators, bias circuits, and calibration loops.
Translate link-level requirements into circuit specifications and optimize performance across PVT, mismatch, aging, and extracted parasitics.
Develop behavioral models and support mixed-signal and top-level verification.
Collaborate with layout and signal-integrity teams on physical implementation, channel/package effects, and post-layout signoff.
Support tapeout, silicon bring-up, characterization, debug, and production release.
Document results and participate in technical design reviews.
Required Qualifications
B.S. in Electrical Engineering or a related field with 3+ years of relevant experience, or an M.S. with 1+ years.
Strong analog CMOS, noise, jitter, feedback, signal-integrity, and data-converter fundamentals.
Hands-on transistor-level design experience with high-speed SerDes circuits.
Excellent command of Cadence Virtuoso, Spectre, Spectre RF, ADE, parasitic extraction, and mixed-signal verification flows.
Strong analytical, communication, collaboration, and engineering judgment.
Preferred Qualifications
Experience with PAM4/NRZ SerDes, advanced CMOS or FinFET technologies, and standards such as Ethernet, PCIe, or CXL.
MATLAB or C for architecture development; SystemVerilog or Verilog-A for functional modeling; and Perl or Python for automation.
Experience using AI-assisted engineering tools responsibly for design exploration, verification, debugging, documentation, and workflow automation.
Custom analog layout experience is a plus.
Lab characterization experience is a plus, along with experience taking mixed-signal IP from architecture through tapeout and silicon validation.
Success in This Role
The ideal candidate combines strong circuit intuition, disciplined verification, ownership, and clear communication to deliver reliable, power-efficient SerDes solutions.
Skills Required
- B.S. in Electrical Engineering or a related field with 3+ years of relevant experience
- M.S. in Electrical Engineering or a related field with 1+ years of relevant experience
- Strong analog CMOS, noise, jitter, feedback, signal-integrity, and data-converter fundamentals
- Hands-on transistor-level design experience with high-speed SerDes circuits
- Excellent command of Cadence Virtuoso, Spectre, Spectre RF, ADE, parasitic extraction, and mixed-signal verification flows
- Strong analytical, communication, collaboration, and engineering judgment
- Experience with PAM4 or NRZ SerDes, advanced CMOS or FinFET technologies, and Ethernet, PCIe, or CXL standards
- MATLAB or C for architecture development; SystemVerilog or Verilog-A for functional modeling; Perl or Python for automation
- Experience using AI-assisted engineering tools for design exploration, verification, debugging, documentation, and workflow automation
- Custom analog layout experience
- Lab characterization experience and experience taking mixed-signal IP from architecture through tapeout and silicon validation
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
-
Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
-
Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
-
Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
Cadence Design Systems Insights
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
