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Develop compiler technology for the Cadence Palladium emulation platform. Responsibilities include solving large-scale compilation problems involving logic optimization, distributed computing, multithreading, distributed databases, and precompiler technologies. The role requires strong software engineering, data structures, algorithms, C/C++ programming, debugging, and Linux/Unix development skills, along with familiarity with hardware description languages and electronic design platforms.

Support Cadence Conformal products, especially equivalency checking, by troubleshooting customer issues, debugging systematically, identifying workarounds, and translating findings for R&D. Collaborate with customers and R&D on product features, enhancements, and solutions. Apply RTL synthesis and verification knowledge, scripting skills in Tcl and Perl, technical writing, and strong communication to meet deadlines and resolve ambiguous problems.

Build pipelines that extract product knowledge from source code, APIs, file formats, and documentation into structured knowledge stores. Design ontologies, schemas, and knowledge graphs; develop parsers, typed interfaces, retrieval systems, and RAG layers; and decompose complex engineering workflows into callable operations. The role collaborates with domain engineers across multiple products and evaluates data quality, coverage, and schema completeness.

Leads a processor design verification team responsible for verifying microprocessor cores and peripherals. Develops verification plans, simulation and emulation testbenches, diagnostics, assertions, coverage monitors, and automated verification flows. Drives coverage closure, collaborates with design, architecture, firmware, and verification teams, and manages work reporting for 7–10 engineers. Requires deep CPU architecture, SystemVerilog, UVM, gate-level simulation, assembly programming, and design verification leadership experience.

Develop and improve UPF compilation software for Palladium and Protium platforms, focusing on performance, correctness, IEEE 1801 support, low-power verification flows, and documentation. Collaborate with R&D, PE, and AE teams to deploy UPF solutions across emulation and prototyping workflows. Contribute to compiler unification, self-checks, example-driven validation, and support for SystemVerilog, Verilog, and VHDL-based designs.

Lead architecture, development, and execution for Conformal logical equivalence checking and ECO technologies. Drive formal verification, scalability, performance, quality, debugging, and AI-powered innovation. Guide complex technical initiatives, resolve customer escalations, influence product strategy, collaborate across engineering and product teams, mentor senior engineers, and engage strategic semiconductor customers and partners.

Lead development of low-power verification software for Cadence Palladium and Protium platforms. Responsibilities include enhancing UPF debugging, event logging, violation detection, IEEE 1801 support, documentation, AI-assisted debugging tools, and unified workflows across emulation and prototyping environments. The role requires collaboration with R&D, product engineering, and applications engineering teams, along with strong debugging, C++ code comprehension, RTL language knowledge, technical writing, and communication skills.

Build and manage sales pipelines for Design IP technology across North American accounts. Drive market penetration, adoption, revenue, and strategic sales plans while managing complex $1M+ licensing deals. Collaborate with engineering, marketing, legal, finance, executives, and EDA sales teams. Develop customer relationships from startups to enterprises, articulate IP value propositions, negotiate contracts, meet revenue targets, and provide market feedback to product leadership.

Develop and troubleshoot multithreaded, distributed physical synthesis software for Cadence’s Innovus platform. Collaborate with global R&D teams, product engineering, and technical sales to deliver customer solutions and workarounds. The role requires C/C++ development in Linux, strong data structures and algorithms knowledge, and customer communication skills. Experience with physical synthesis, timing analysis, multithreading, IC physical design tools, design closure, physical design flows, Tcl, and scripting is preferred.

Technical leader for Cadence’s Voltus power integrity and reliability platform. Owns advanced-node IR/EM signoff enablement, foundry and customer requirements, complex SoC/PDN issue resolution, modeling, product roadmap influence, and deployment. Partners across R&D, applications, field teams, marketing, customers, and foundries while mentoring engineering teams. Requires deep EMIR, PDN, digital physical implementation, CMOS, low-power design, scripting, and customer-facing technical leadership experience.