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Provide technical sales support as a senior application engineer for signal and power integrity across IC, package, and PCB designs. Deliver workshops, demos, training, and onsite customer support; analyze customer environments and recommend EDA solutions using Cadence or competitive tools. Collaborate with sales, R&D, product engineering, and marketing to ensure customer success.

Develop and debug bare-metal firmware for DDR5 PHY microcontrollers, collaborate with hardware designers and verification teams to implement training algorithms, perform firmware-hardware co-verification in RTL simulations, and support silicon bring-up and debugging using EDA tools and scripting.

Design-for-Test (DFT) engineer responsible for scan chain and compression insertion, MBIST/LBIST, ATPG pattern generation and verification, debugging failures, verifying ATPG testbenches, and collaborating across architecture, design, and customer teams. Work with JTAG/IEEE test standards and Cadence flows to meet test coverage and quality metrics.

Lead research, design, development, and validation of advanced nonlinear finite element analysis algorithms and solution capabilities for MSC Nastran/Marc. Implement, optimize, test, benchmark, and document FEA features; create verification models and automated regression tests; investigate defects and performance issues; support QA, release readiness, and cross-team collaboration while mentoring engineers and guiding architectural decisions.

Serve as a technical pre-sales leader, driving cross-functional campaigns that match Cadence digital design and EDA solutions to customer needs. Build relationships with customer engineering and leadership, influence buying decisions, manage complex technical projects, and support multi-million-dollar sales through technical expertise across the RTL-to-GDSII flow and AI/ML optimization methods.

Lead customer technical engagement for Digital/Custom/Analog/RF design flows (Innovus, Virtuoso), drive adoption of advanced layout and AI-driven automation, translate customer needs to R&D, and expand Cadence Custom IC footprint while supporting executive-level discussions and methodology definition.

Provide administrative support to HR leadership: manage complex calendars across time zones, coordinate domestic and international travel, organize events and meetings, prepare expense reports and purchase requisitions, support special projects, and handle confidential communications while building cross-functional relationships.

Develop software solutions, analyze algorithms, collaborate on architecture, code review, and document design. Requires strong C/C++ proficiency and problem-solving skills.

The Principal Product Engineer will develop and drive customer adoption of AI-driven Layout Automation flows, focusing on analog layout expertise and automation technology, while collaborating with customers.

Develop and maintain EDA tools for transistor-level analysis. Enhance architecture for timing analysis and implement machine learning technologies for improved solutions.