Design Verification Architect / Director

Posted 11 Days Ago
Be an Early Applicant
2 Locations
In-Office
186K-345K Annually
Expert/Leader
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Leads a processor design verification team responsible for verifying microprocessor cores and peripherals. Develops verification plans, simulation and emulation testbenches, diagnostics, assertions, coverage monitors, and automated verification flows. Drives coverage closure, collaborates with design, architecture, firmware, and verification teams, and manages work reporting for 7–10 engineers. Requires deep CPU architecture, SystemVerilog, UVM, gate-level simulation, assembly programming, and design verification leadership experience.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Location

San Jose, CA and Austin, TX

Job Description

Responsibilities 

As a Design Verification Team Director, lead and run the Processor Verification team, you will be responsible for the verification of microprocessor cores and their peripherals

Relevant experience in-order/out-of-order CPU cores and memory subsystem strongly preferred 

Crafting verification plans and executing them to verify highly complex CPU designs.

You will implement simulation or emulation testbenches, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals.

You will be responsible for coverage collection and closure

You will work closely with cross-functional teams (DV/Arch/Design/FW) to identify coverage scope

Tracking and reporting the work of 7-10 engineers

Required Skills and Experience:

17+ years of design verification experience

BS (or higher) in EE/Computer Engineering

Proven experience at leading/managing team.

Strong managerial, leadership and interpersonal skills

Excellent knowledge of computer architecture and design verification fundamentals

Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenches

Exposure to scripting languages like Perl, Unix shell or similar languages

Experience with assembly language programming required

Experience with Formal Verification will be a plus

Experience with the development of fully automated flows

Experience with Gate Level Simulations

Excellent written and oral communication skills necessary

Knowledge of processor verification required

The annual salary range for California is $185,500 to $344,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • 17+ years of design verification experience
  • Bachelor’s degree or higher in Electrical Engineering or Computer Engineering
  • Proven experience leading or managing a team
  • Strong managerial, leadership, and interpersonal skills
  • Excellent knowledge of computer architecture and design verification fundamentals
  • Thorough understanding of SystemVerilog and UVM
  • Experience with programming languages for building complex testbenches
  • Experience with scripting languages such as Perl or Unix shell
  • Assembly language programming experience
  • Experience developing fully automated verification flows
  • Experience with gate-level simulations
  • Knowledge of processor verification
  • Experience with in-order or out-of-order CPU cores and memory subsystems
  • Formal verification experience

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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