Join our team and help build the next generation of low-power verification software for the Palladium and Protium emulation and prototyping platforms.
As a Lead Software Engineer - Low Power Verification you will be responsible for improving the performance and usability of UPF debug features, adding support for new IEEE 1801 LRM revisions, and rebuilding UPF documentation around end-to-end workflows for multi-billion-gate low-power designs.
What you will do:
Enhance UPF debug features -- improve performance and usability across the Parallel Partition Compiler (PPC) and Modular Compiler (MC) flows, including Dielet UPF support.
Scale UPF event logging and violation detection – apply new techniques to capture and report more UPF events, with better multi-billion-gate low-power designs.
Rebuild UPF documentation around end-to-end debug scenarios and workflows, backed by valid SystemVerilog and UPF examples.
Help develop AI-assisted UPF debug tools to reduce time-to-root-cause for low-power design issues.
Work with R&D, PE and AE teams to deploy UPF solutions across key flows (AVIP, UVMA, MC, and Dielets -- each with UPF in 2- and 4-state).
Help consolidate and unify UPF debug across Palladium and Protium.
What we are looking for
- BS in CS, EE, or a related field with 4+ years of experience; MS with 2+ years; PhD with 1+ year; or equivalent practical experience.
- Working knowledge of IEEE 1801 UPF and RTL languages (Verilog, SystemVerilog, VHDL).
- Strong debugging skills — root-cause analysis from logs, waveforms, traces, testcases, and user reports.
- Ability to read, review, and reason about C++ code and object-oriented designs.
- Fluency with AI-assisted coding tools (Copilot, Claude, Cursor, or equivalent), with critical evaluation of AI output.
- Strong communication and technical writing skills — able to turn scattered debug evidence into clear, user-facing workflows.
The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.Skills Required
- Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 4+ years of experience
- Master’s degree with 2+ years of experience
- PhD with 1+ year of experience
- Equivalent practical experience
- Working knowledge of IEEE 1801 UPF
- Working knowledge of Verilog, SystemVerilog, and VHDL
- Strong debugging and root-cause analysis skills using logs, waveforms, traces, test cases, and user reports
- Ability to read, review, and reason about C++ code and object-oriented designs
- Fluency with AI-assisted coding tools such as Copilot, Claude, Cursor, or equivalent
- Strong communication and technical writing skills
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
Cadence Design Systems Insights
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
