This Senior Principal Product Engineer is a technical leader on the Voltus product engineering team, working on Cadence’s power noise and reliability analysis platform. The role sits between strategic customers/foundries, Applications, and R&D, and is accountable for turning the hardest IR/EM, PDN, and electrothermal signoff requirements into product and flow solutions.
Key responsibilities
- Serve as the primary technical interface to R&D for Voltus, driving product requirements, priorities, and methodology for strategic foundry and customer programs.
- Lead Voltus enablement for advanced-node IR/EM signoff: flow/techfile/PDK readiness, reference flows, qualification, benchmarking, and production deployment.
- Own resolution of complex customer issues spanning static/dynamic IR, EM, low-power / multi-voltage domains, hierarchical and full-chip signoff, and related timing/stack-die interactions.
- Define and validate foundry-aligned power integrity and EM modeling assumptions; partner with PDK, extraction, and signoff teams on advanced-node and 3DIC readiness.
- Influence product roadmap (including AI-driven IR mitigation, 3DIC, and electrothermal co-analysis) based on foundry and customer gaps.
- Mentor Lead/Principal PEs and AEs; set debug standards, deployment practices, and issue-tracking discipline for the account/foundry program.
- Work effectively with customers, Cadence field, Marketing, and R&D across geographies; present findings and recommendations to customer and internal leadership.
Minimum qualifications
- Bachelor’s in Electrical / Electronics / VLSI Engineering with 10+ years of related experience, or MS with 8+ years, or PhD with 6+ years.
- Deep hands-on experience with industry-standard IR/EM (EMIR) and PDN analysis tools and digital physical implementation / signoff flows.
- Strong background in CMOS/digital design, power IR-drop analysis, circuit analysis, and low-power / multi-power-domain chip power-integrity signoff.
- Proven ability to separate critical issues from noise, debug large SoC/PDN problems, and close the loop from customer requirement to R&D fix to deployment.
- Scripting in Tcl and Python; strong written, verbal, and presentation skills with customer and executive audiences.
Preferred
- Direct experience with Voltus and adjacent Cadence digital signoff/implementation tools (Integrity, Tempus, Innovus, Quantus/QRC).
- 3DIC / chiplet, electrothermal, and advanced FinFET or GAA node experience.
- Prior technical leadership of PE/AE teams or of a strategic account/foundry program.
The annual salary range for California is $161,000 to $299,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.Skills Required
- Bachelor’s degree in Electrical, Electronics, or VLSI Engineering with 10+ years of related experience; alternatively, an MS with 8+ years or PhD with 6+ years
- Deep hands-on experience with industry-standard IR/EM and PDN analysis tools and digital physical implementation or signoff flows
- Strong background in CMOS/digital design, power IR-drop analysis, circuit analysis, and low-power or multi-power-domain chip power-integrity signoff
- Ability to debug large SoC/PDN problems and translate customer requirements into R&D fixes and deployment solutions
- Scripting experience in Tcl and Python
- Strong written, verbal, and presentation skills with customer and executive audiences
- Direct experience with Voltus and adjacent Cadence digital signoff or implementation tools, including Integrity, Tempus, Innovus, or Quantus/QRC
- Experience with 3DIC/chiplet, electrothermal analysis, or advanced FinFET/GAA nodes
- Prior technical leadership of PE/AE teams or a strategic account/foundry program
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
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What We Do
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