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As a Senior ASIC Verification Engineer, you will verify the design and implementation of SoCs, collaborate with teams, and innovate verification workflows, ensuring first-pass silicon success.

As a DFT Engineer, you will work on design-for-test solutions for sophisticated semiconductor chips, collaborating with various teams and vendors.

Lead AI software resiliency development, implementing features for reliability and fault tolerance in large-scale AI supercomputers, requiring hands-on coding and collaboration.

Lead device and SPICE modeling efforts, collaborate with foundries on device development, and validate models through test structures and simulations.

Responsible for FPGA/CPLD design including micro-architecture, RTL coding, logic debug, timing closure, and collaboration with various teams for validation and implementation.

The role involves creating Signal and Power Integrity solutions, system-level simulations, and collaborating with design teams on power delivery networks.

Define and design GPU and SoC-based products, guide design engineers, balance cost and performance, and manage project timelines.

The role involves driving physical design from netlist to GDS, working on timing closure, physical verification, and collaborating with mixed signal teams. Candidates should have experience in Synopsys or Cadence tools and physical design.

The role involves defining and productizing the operational standards for enterprise AI infrastructure, focusing on seamless integration, management, and automation of DGX systems in private data centers.

The Senior Network Reliability Engineer will support cloud and datacenter networks, manage incidents, engage with vendors, and drive operational improvements.