Top Tech Jobs & Startup Jobs

Develop algorithms and optimizations for inference and compiler stack, enhance performance metrics, collaborate with hardware teams, and publish work on novel approaches.

Own and implement DFT architectures and test access mechanisms (IEEE standards, memory BIST, scan, memory dump, DFX security); architect and deploy DFT methodologies across RTL, verification, and pattern generation; collaborate with timing, physical design, software, bringup and production teams; perform silicon debug and ATE bring-up; mentor junior engineers on test design trade-offs.

Lead design and deployment of advanced silicon test methodologies, own cross-functional implementation of scan, BIST, and scan compression, and drive chip bring-up from pre-silicon to production. Develop standardized bring-up processes, mentor junior engineers, collaborate with VLSI and product teams, and validate test patterns and debug silicon failures.

Develop and improve NVIDIA GPU compiler back end: investigate issues, implement code generation improvements, and collaborate with global compiler, hardware, and application teams to emit high-performance GPU machine instructions for graphics and compute workloads.

The Senior Mask Layout Design Engineer will perform physical layout for mixed-signal designs, collaborate with engineers, and ensure compliance with design rules.

Drive physical design for CPUs, GPUs, and SoCs, focusing on netlist aspects, timing convergence, and utilizing EDA tools for high-frequency, low-power designs.

The role involves developing device drivers for network interface cards, optimizing software solutions, and addressing complex technical issues in the Linux kernel group.

Operate and improve an AI Data Center AIOps platform: monitor health, own SLOs/SLIs, handle incidents, manage Kubernetes deployments, maintain IaC/CI-CD (Helm/Terraform), and produce runbooks/automation to ensure reliability and scalable telemetry processing.

Responsible for developing incident management guidelines, supporting production systems, defining reliability metrics, and driving automation for high service availability.

Drive efficiency in High-Speed IO engineering through automation, improve verification flows, collaborate with engineers, and enhance productivity metrics.