Top Tech Jobs & Startup Jobs

Design and deliver OS-level and container platform features integrated with ESXi and vSphere. Architect scalable container runtimes, Kubernetes platform capabilities, and distributed control planes. Develop and optimize user-space OS services, contribute security fixes upstream, collaborate with product, UX, and cross-functional teams to produce reliable, high-performance infrastructure for cloud-native workloads.

Lead SoC DFT programs from specification through implementation, verification, and production release. Responsibilities include DFT architecture, scan/ATPG insertion and compression, pattern generation, ATE validation and silicon debug, yield improvement, STA cooperation, customer interfacing, and automation of DFT and vector-generation flows.

Design and verify CMOS I/Os and analog/mixed-signal blocks (bandgap references, op-amps, comparators, POR). Run SPICE/Spectre simulations for AC/DC, SI, jitter, and power. Perform transistor reliability/EM/IR analysis, build Verilog/Liberty/IBIS models, collaborate with layout for physical design and verification, produce technical documentation, and support chip integration and silicon bring-up.

Lead top-level chip floorplanning and partitioning, manage clock tree and I/O/bump planning, resolve physical-design integration and DRC/LVS/EMIR issues, collaborate with package/methodology teams, and develop/improve floorplanning methodologies and vendor/IP evaluations.

Provide pre- and post-sales technical support for high-speed interconnect PHY products, debug hardware/firmware/board issues, review schematics/layouts, analyze customer architectures, train customers and FAEs, and support product definition and roadmap to secure customer design wins.

Lead and manage external customer ASIC programs end-to-end, advise on EDA flows and best practices, perform physical design and STA checks, identify and mitigate design risks, coordinate cross-functional teams (test, packaging, fabrication, bring-up), and communicate technical findings to management and business teams.

Lead and manage customer ASIC programs end-to-end, advise on EDA flows and design best practices, execute physical design checks, assess and mitigate risks, collaborate with cross-functional teams, and support tape-out, bring-up, and production for advanced-node chips.

Lead chip-level digital architecture, own top-level RTL and integration, drive timing/CDC constraints and front-end flows, coordinate cross-discipline teams through tape-out, and mentor engineers while supporting post-silicon bring-up and validation.

Customer-facing architect for VMware Cloud Foundation and vKS who designs and validates SDDC deployments, integrates physical underlay (Cisco ACI) with NSX overlays, architects Kubernetes networking and enterprise load balancing (AVI, F5, Netscaler), leads discovery workshops and POCs, and produces reusable reference architectures to accelerate private cloud adoption.

Develop and maintain verification environments using SystemVerilog and UVM/OVM; create UVM agents, behavioral models, assertions, coverage; write random and directed tests; analyze/debug simulation failures and coverage; collaborate with design teams to resolve complex verification issues.