Senior Custom ASIC Engineering Lead

Posted Yesterday
Be an Early Applicant
3 Locations
In-Office
144K-230K Annually
Senior level
Software • Semiconductor • Manufacturing
The Role
Lead and manage external customer ASIC programs end-to-end, advise on EDA flows and best practices, perform physical design and STA checks, identify and mitigate design risks, coordinate cross-functional teams (test, packaging, fabrication, bring-up), and communicate technical findings to management and business teams.
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Job Description:

Are you a versatile, senior engineer capable of leading external and internal cross-functional teams in areas such as physical design, STA, DFT, and packaging? Have you taped out so many chips that you can identify potential design problems hidden in EDA reports, advise design teams on how to fix them, and then publish an application note about avoiding them in future? Do you love technical-deep-dive with engineers and providing an eagle’s eye summary to management? If this is your engineering profile and you are looking for a challenge, then we have one for you.

Broadcom develops critical Infrastructure chips that enable a variety of Customers to produce ASICs in almost all major segments of the Semiconductor industry, including AI. Our ASIC Products Division is looking for a senior engineer to guide customer teams designing challenging chips in areas such as AI, HPC, networking and storage. This is an immensely responsible position, and an opportunity to push the frontiers of technology by working with cross-functional teams inside and outside of Broadcom.

As a valued member of this team, you will be required to do the following:

  • Manage external customer ASIC programs from inception to finish, including RFQs, technology and IP collaterals, design, test, packaging, fabrication, bring-up and production

  • Advise customers on best practices in EDA, flows and design methodologies, and by organizing Q&A sessions with Broadcom technology experts

  • See ahead, plan ahead, work ahead. Proactively assess potential risks to the design quality and project schedule, then work with cross-functional teams to prepare and execute risk mitigation actions

  • Execute physical design flows to check that incoming customer tape-in netlists meet Broadcom’s stringent tape-out quality standards

  • Motivate and drive yourself to stay abreast of developments in Broadcom IPs, technology and end user applications

  • Participate in discussions about your chips with marketing, sales, legal and regulatory compliance teams

  • Be a consummate team player and assist other teams in need

You must have these proven skills to qualify for this position:

  • Multiple tape-outs in advanced technology nodes

  • Analyze PPA tradeoffs involved amongst various library components, and architectures

  • Knowledgeable in low power design and power management

  • Hands-on experience in physical design and STA, EDA tools, design flows for physical design, logic simulation, test, and packaging

  • Programming in TCL, shell and scripting languages

Following skills are nice to have:

  • Exposure to SERDES communications protocols.

  • Logic design, chip architecture, microarchitecture, Verilog RTL coding Front-end logic design verification, DRC, logic synthesis

  • Knowledge of DFT methods including scan, memory BIST and repair

Education and Experience Requirements:

  • Bachelors degree and 12+ years of related experience; or Masters degree and 10+ years of related experience

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $143,800 - $230,000. 

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Skills Required

  • Multiple tape-outs in advanced technology nodes
  • Analyze PPA tradeoffs among library components and architectures
  • Knowledge of low power design and power management
  • Hands-on experience in physical design and STA, EDA tools, and physical design flows
  • Experience with logic simulation, test methodologies, and packaging
  • Programming in TCL, shell and scripting languages
  • Bachelors degree and 12+ years related experience or Masters degree and 10+ years related experience
  • Manage customer ASIC programs from RFQ through production, including technology/IP collaterals and fabrication
  • Proactively assess design quality and schedule risks and lead mitigation actions
  • Ability to engage cross-functional teams and communicate with marketing, sales, legal, and compliance
  • Exposure to SERDES communications protocols
  • Logic design, chip architecture, microarchitecture, Verilog RTL coding, front-end verification, DRC, logic synthesis
  • Knowledge of DFT methods including scan, memory BIST and repair

Broadcom Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Broadcom and has not been reviewed or approved by Broadcom.

  • Equity Value & Accessibility Equity is used broadly through RSUs with quarterly or annual vesting, and an ESPP with a discount and look‑back that can add meaningful upside. Company disclosures show ongoing equity grants, including inducement RSUs tied to acquisitions, underscoring equity’s central role in total rewards.
  • Retirement Support A 401(k) plan with a competitive company match and immediate vesting is consistently highlighted, supporting long‑term savings. Tax‑advantaged accounts like HSA/FSA further strengthen the financial wellness toolkit.
  • Pay Growth & Progression Compensation ceilings in technical tracks are described as high, with wide ranges and very strong totals for experienced engineers. Sales compensation is also characterized as competitive, supporting attractive on‑target earnings.

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The Company
HQ: San Jose, CA
38,985 Employees
Year Founded: 1991

What We Do

Broadcom Inc. (NASDAQ: AVGO) is a global technology leader that designs, develops and supplies semiconductor and infrastructure software solutions.

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