DFT Lead Engineer

Posted 11 Days Ago
Be an Early Applicant
San Jose, CA, USA
In-Office
144K-230K Annually
Expert/Leader
Software • Semiconductor • Manufacturing
The Role
Lead SoC DFT programs from specification through implementation, verification, and production release. Responsibilities include DFT architecture, scan/ATPG insertion and compression, pattern generation, ATE validation and silicon debug, yield improvement, STA cooperation, customer interfacing, and automation of DFT and vector-generation flows.
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Job Description:

Principal DFT Engineer

Broadcom's ASIC Product Division is seeking candidates for a DFT position at our San Jose, California, Development Center. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production.

The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Products Division)’s designs – DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers.

It is expected that you can code using TCL, PERL, RUBY, PYTHON, C++ or similar.

Responsibilities:

  • Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC

  • Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration

  • Working closely with STA and DI Engineers design closure for test

  • Generating, Verifying & Debugging Test vectors before tape release.

  • Validating & Debugging Test vectors on ATE during the silicon bring up phase

  • Assisting with silicon failure analysis, diagnostics & yield improvement efforts

  • Interfacing with the customer, physical design and test engineering/manufacturing teams located globally

  • Working closely with I/P DFT engineers & other stakeholders

  • Debugging customer returned parts on the ATE

  • Innovating newer DFT solutions to solve testability problems in 7nm & beyond

  • Automating DFT & Test Vector Generation flows

 Skills/Experience:

  • Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)

  • Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.)

  • Well-versed in ATPG vector generation, simulation, and  debugging. (TetraMax, Fastscan)

  • Experience in Verilog coding, testbench generation & simulation

  • Memory BIST insertion and verification experience on embedded  (SRAM, CAM, eDRAM, ROM)

  • Boundary scan Verification and test vector generation. Should have good knowledge in IEEE1149.1 and IEEE1149.6

  • Basic knowledge Test-STA and constraints

  • Strong background on IEE1687, IJTAG, ICL and PDL 

  • The ability to work in a multi-disciplined, cross-department environment

  • Solid knowledge in analog and digital circuit design, and device physics fundamentals

  • Good understanding of Si processing, logical and physical synthesis, and transistor reliability principles

  • Excellent problem solving, debug, root cause analysis and communication skills

  • Experience working on the ATE is a plus

  • Experience with Serdes, DDR, PCIE, ENET, CXL IOBIST verification and silicon debug is a plus

  • Experience working on Tessent SSN is highly desired

Education & Experience:

  • Bachelors in Electrical/Electronic/Computer Engineering and 12+ years of relevant industry experience or Masters Degree in Electrical/Electronic/Computer Engineering and 10+ years of relevant industry experience


Compensation and Benefits


The annual base salary range for this position is USD 143,800.00 To USD 230,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.


Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.


Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.


If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Skills Required

  • Strong DFT background (IO/Analog DFT, ATPG, Scan, BIST)
  • Experience with scan insertion and scan compression (DFT Compiler, Mentor TestKompress)
  • ATP G vector generation, simulation, and debugging (TetraMax, Fastscan)
  • Verilog coding, testbench generation and simulation
  • Memory BIST insertion and verification for embedded memories (SRAM, CAM, eDRAM, ROM)
  • Boundary-scan verification and test vector generation; knowledge of IEEE1149.1 and IEEE1149.6
  • Knowledge of IEEE1687/IJTAG, ICL and PDL
  • Basic knowledge of Test-STA and timing constraints
  • Solid analog and digital circuit design and device physics fundamentals
  • Understanding of silicon processing, logical/physical synthesis, and transistor reliability
  • Ability to debug test vectors on ATE and assist silicon failure analysis and yield improvement
  • Proficiency coding/scripting (TCL, PERL, RUBY, Python, C++) for automation
  • Experience interfacing with customers and cross-functional global teams
  • Experience with ATE
  • Experience with SerDes, DDR, PCIe, Ethernet, CXL IOBIST verification and silicon debug
  • Experience with Tessent SSN
  • Bachelor's in EE/CE with 12+ years or Master's with 10+ years relevant industry experience

Broadcom Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Broadcom and has not been reviewed or approved by Broadcom.

  • Equity Value & Accessibility Equity is used broadly through RSUs with quarterly or annual vesting, and an ESPP with a discount and look‑back that can add meaningful upside. Company disclosures show ongoing equity grants, including inducement RSUs tied to acquisitions, underscoring equity’s central role in total rewards.
  • Retirement Support A 401(k) plan with a competitive company match and immediate vesting is consistently highlighted, supporting long‑term savings. Tax‑advantaged accounts like HSA/FSA further strengthen the financial wellness toolkit.
  • Pay Growth & Progression Compensation ceilings in technical tracks are described as high, with wide ranges and very strong totals for experienced engineers. Sales compensation is also characterized as competitive, supporting attractive on‑target earnings.

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The Company
HQ: Palo Alto, CA
38,985 Employees
Year Founded: 1991

What We Do

Broadcom Inc. (NASDAQ: AVGO) is a global technology leader that designs, develops and supplies semiconductor and infrastructure software solutions.

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