Top Tech Jobs & Startup Jobs

Perform deep-dive research into emerging network threats and architect AI-enabled detection solutions. Analyze malicious traffic, design and implement high-performance IDPS/IDS signatures, and build scalable data collection and enrichment pipelines. Translate threat intelligence into actionable, high-fidelity detection logic and prototypes while collaborating with a global team.

Design and verify high-speed SerDes physical-layer algorithms and architectures (100G+). Develop bit-exact MATLAB and C/C++ system models, run system-level simulations, collaborate with analog/digital teams, perform lab validation and firmware/debug, document requirements and test plans, support standards and customer interactions.

Provide technical support for Broadcom mainframe products (Endevor/Zowe), troubleshoot complex customer issues, analyze logs, recreate problems in lab environments, share KCS knowledge, mentor junior engineers, participate in scrum and product quality activities, and occasionally travel/on-call as required.

Lead product vision, strategy, and roadmap for a mainframe network management product (NetMaster). Work with Product Owner, R&D, architecture, and sales to prioritize features, drive customer validation, enable GTM, measure adoption, and remove cross-team roadblocks. Engage customers through meetings and conferences to inform product decisions.

Lead ownership and improvement of wafer-level test tool groups for MEMS/silicon devices. Specify, install, program, qualify and maintain probers/testers, ensure measurement accuracy and repeatability, drive continuous improvement projects, investigate yield and tool incidents, collaborate with cross-functional fab teams, and develop procedures, FMEAs, and monitoring (FDC/MES) for production and R&D.

Design and verify memory compilers and custom memory macros (SRAM, register-files, ROM). Perform transistor-level design and simulation, layout extraction, post-layout verification, floorplanning and physical integration, characterization and automation, silicon test plan definition, and silicon debug. Document specifications and models.

Design and deliver OS-level and container platform features integrated with ESXi and vSphere. Architect scalable container runtimes, Kubernetes platform capabilities, and distributed control planes. Develop and optimize user-space OS services, contribute security fixes upstream, collaborate with product, UX, and cross-functional teams to produce reliable, high-performance infrastructure for cloud-native workloads.

Lead SoC DFT programs from specification through implementation, verification, and production release. Responsibilities include DFT architecture, scan/ATPG insertion and compression, pattern generation, ATE validation and silicon debug, yield improvement, STA cooperation, customer interfacing, and automation of DFT and vector-generation flows.

Design and verify CMOS I/Os and analog/mixed-signal blocks (bandgap references, op-amps, comparators, POR). Run SPICE/Spectre simulations for AC/DC, SI, jitter, and power. Perform transistor reliability/EM/IR analysis, build Verilog/Liberty/IBIS models, collaborate with layout for physical design and verification, produce technical documentation, and support chip integration and silicon bring-up.

Lead top-level chip floorplanning and partitioning, manage clock tree and I/O/bump planning, resolve physical-design integration and DRC/LVS/EMIR issues, collaborate with package/methodology teams, and develop/improve floorplanning methodologies and vendor/IP evaluations.