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Reposted 19 Days AgoSaved
In-Office
San Jose, CA, USA
110K-176K Annually
Mid level
110K-176K Annually
Mid level
Software • Semiconductor • Manufacturing
This role focuses on modeling and simulation of piezoelectric resonators, requiring close collaboration with cross-functional teams to optimize device performance using FEM models in Comsol.
Top Skills: AdsComsolHfssMatlabPython
Reposted 19 Days AgoSaved
In-Office or Remote
Location, WV, USA
Expert/Leader
Expert/Leader
Software • Semiconductor • Manufacturing
The Manager, Solution Engineer will lead a team in pre-sales for VMware Cloud Foundation, focusing on technical strategy, team development, and driving customer adoption.
Top Skills: Avi Load BalancerAWSAzureCcieGCPNetworking & SecurityNsxRed Hat OpenshiftVdefendVmware Cloud FoundationVsphere Kubernetes Services
Reposted 19 Days AgoSaved
In-Office
San Jose, CA, USA
101K-162K Annually
Senior level
101K-162K Annually
Senior level
Software • Semiconductor • Manufacturing
The Senior Reliability Engineer will develop and execute tests for RF devices, focusing on performance stability, reliability, and failure analysis in semiconductor products.
Top Skills: Esd CharacterizationRf Cmos TechnologyRf TestingSemiconductor Device ReliabilityThermal Testing
Reposted 19 Days AgoSaved
In-Office
San Jose, CA, USA
120K-192K Annually
Senior level
120K-192K Annually
Senior level
Software • Semiconductor • Manufacturing
Join Broadcom's Core Switching Group as an Applications Engineer to enhance customer support workflows using AI capabilities and modern programming languages.
Top Skills: BigQueryCDialogflow CxJavaScriptLlm ApisPythonVertex Ai
Reposted 19 Days AgoSaved
In-Office
Warrenville, IL, USA
91K-146K Annually
Senior level
91K-146K Annually
Senior level
Software • Semiconductor • Manufacturing
The SDET plans, designs, develops, and executes tests across software enhancements. Responsibilities include automation, collaboration in Agile teams, and ensuring high-quality software delivery.
Top Skills: Ci/CdJavaScriptJenkinsJmeterPythonRest Api
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21 Days AgoSaved
In-Office
San Jose, CA, USA
144K-230K Annually
Expert/Leader
144K-230K Annually
Expert/Leader
Software • Semiconductor • Manufacturing
Develop and maintain verification environments using SystemVerilog and UVM/OVM; create UVM agents, behavioral models, assertions, coverage; write random and directed tests; analyze/debug simulation failures and coverage; collaborate with design teams to resolve complex verification issues.
Top Skills: AsicBus ProtocolsCC++CoverageCpuDdrDspEmulatorsFpga PrototypingNetwork ProtocolsOvmPerlRtlSocSystemcSystemverilogSystemverilog AssertionsUvm
21 Days AgoSaved
In-Office
3 Locations
144K-230K Annually
Senior level
144K-230K Annually
Senior level
Software • Semiconductor • Manufacturing
Lead and manage customer ASIC programs end-to-end, advise on EDA flows and design best practices, execute physical design checks, assess and mitigate risks, collaborate with cross-functional teams, and support tape-out, bring-up, and production for advanced-node chips.
Top Skills: DftEda ToolsLogic SimulationPackagingPhysical DesignScripting LanguagesShellStatic Timing Analysis (Sta)TclTest
21 Days AgoSaved
In-Office
San Jose, CA, USA
144K-230K Annually
Expert/Leader
144K-230K Annually
Expert/Leader
Software • Semiconductor • Manufacturing
Lead chip-level digital architecture, own top-level RTL and integration, drive timing/CDC constraints and front-end flows, coordinate cross-discipline teams through tape-out, and mentor engineers while supporting post-silicon bring-up and validation.
Top Skills: AtpgBoundary ScanCadenceCdcDdrDesign CompilerDftGenusJaspergoldLintPciePerlPrimetimePythonSdcSerdesSpyglassStatic Timing Analysis (Sta)SynopsysSystemverilogTclTempusVerilog
21 Days AgoSaved
In-Office
San Jose, CA, USA
144K-230K Annually
Expert/Leader
144K-230K Annually
Expert/Leader
Software • Semiconductor • Manufacturing
Lead full physical IC design flow from RTL to tape-out including synthesis, place-and-route, clock tree synthesis, timing closure, EM/IR analysis, floorplanning, and physical verification. Develop flows and methodologies, collaborate with RTL designers, and perform EDA tool scripting and automation. On-site role at San Jose.
Top Skills: Clock Tree SynthesisEda ToolsEm/Ir AnalysisPciePerlPhysical VerificationPlace And RouteRtlSynthesisTclTiming Closure
Reposted 21 Days AgoSaved
In-Office
3 Locations
110K-176K Annually
Senior level
110K-176K Annually
Senior level
Software • Semiconductor • Manufacturing
Develop and maintain software solutions for mainframe products, participate in agile development, and engage in code and test plan reviews.
Top Skills: AsmCC++CobolIbm AssemblerJclMetal ClPythonRexxTsoZ/OsZ/Os Language Environment
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