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Perform full-chip physical IC design from RTL to tape-out including synthesis, place-and-route, timing closure, clock tree synthesis, floorplanning, EM/IR analysis, physical verification, methodology development, and collaboration with RTL engineers. On-site role in San Jose.

Lead and manage external customer ASIC programs end-to-end, advise on EDA flows and best practices, perform physical design and STA checks, identify and mitigate design risks, coordinate cross-functional teams (test, packaging, fabrication, bring-up), and communicate technical findings to management and business teams.

Lead and manage customer ASIC programs end-to-end, advise on EDA flows and design best practices, execute physical design checks, assess and mitigate risks, collaborate with cross-functional teams, and support tape-out, bring-up, and production for advanced-node chips.

The Design Verification Engineer is responsible for verifying networking ASIC designs, developing test plans, implementing test suites, and ensuring completion through various metrics.

Develop and maintain advanced verification environments using SystemVerilog/UVM/OVM; design UVM agents and behavioral models; implement assertions and coverage; create random and directed tests; debug simulation failures and analyze coverage; collaborate with design teams on SoC/IP verification.

Lead chip-level digital architecture, own top-level RTL and integration, drive timing/CDC constraints and front-end flows, coordinate cross-discipline teams through tape-out, and mentor engineers while supporting post-silicon bring-up and validation.

The ASIC Design Engineer is responsible for leading complex design implementations, ensuring quality through peer reviews, and adapting to technology changes.

Customer-facing architect for VMware Cloud Foundation and vKS who designs and validates SDDC deployments, integrates physical underlay (Cisco ACI) with NSX overlays, architects Kubernetes networking and enterprise load balancing (AVI, F5, Netscaler), leads discovery workshops and POCs, and produces reusable reference architectures to accelerate private cloud adoption.

The ASIC Design Engineer leads design implementations, ensuring quality in multiple disciplines including synthesis, floorplanning, and timing closure with minimal supervision.

Develop and maintain verification environments using SystemVerilog and UVM/OVM; create UVM agents, behavioral models, assertions, coverage; write random and directed tests; analyze/debug simulation failures and coverage; collaborate with design teams to resolve complex verification issues.