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Verify high-speed interconnect ASICs throughout the product lifecycle at block and chip levels. Develop and maintain SystemVerilog UVM verification environments, understand IEEE Ethernet standards, collaborate with architecture, design, and firmware teams, and create scripting tools to improve verification efficiency and design quality.

Designs high-speed ASIC blocks for 10Gbps–400Gbps communication systems. Responsibilities include architecture, RTL/HDL coding, timing constraints, verification, synthesis, equivalency checking, CDC and lint reviews, power and design-for-test analysis, scripting, silicon bring-up, lab debugging, and production qualification. Collaborates with distributed engineering teams to define resources, schedules, validation plans, and design tradeoffs.

Designs and validates ASIC blocks for high-speed optical communication physical-layer products. Responsibilities include architecture, RTL coding, lint, CDC, synthesis, equivalence checking, timing analysis, simulation, silicon debug, verification planning, power and area tradeoffs, silicon bring-up, and ATE validation. Requires expertise in ARM subsystems, high-speed digital design, Ethernet and OTN networks, FEC, ASIC development flows, and design-for-power, test, and manufacturing.

Designs and validates high-speed analog and mixed-signal circuitry for data center connectivity applications. Responsibilities include developing novel CMOS circuit techniques, optimizing speed, power, and area, creating circuit models, performing simulation and custom layout, developing test plans, and characterizing and debugging designs for manufacturability. The role also requires analyzing experimental results, selecting reliable components, and understanding broadband communication SoC architectures.

Executes the full physical IC design cycle from RTL through silicon tape-out, including synthesis, physical verification, timing closure, EM/IR analysis, place and route, clock tree synthesis, floorplanning, layout, and methodology development. Collaborates with RTL design engineers and applies TCL/Perl scripting and EDA tools. This is an in-person role in Colorado Springs, Colorado.

Design and verify analog and mixed-signal IP, including bandgaps, ADCs, DACs, regulators, comparators, and GPIOs. Oversee layout and post-layout SPICE validation, develop Verilog behavioral and gate-level models, deliver EDA views and technical documentation, and guide silicon bring-up and validation. Analyze test data, support laboratory testing, and troubleshoot silicon failures while collaborating across advanced process technologies.

Test engineer responsible for validating PCIe switch functionality, performance, and compliance across configurations. Duties include creating test scenarios and automation, reviewing specifications and documentation, executing tests with distributed development teams, debugging issues, and managing parallel projects and releases. The role requires PCIe protocol expertise, system-level PCIe knowledge, and Python-based network and system programming. Experience with GPUs, AI/ML clusters, NVMe, networking protocols, and PCIe test equipment is advantageous.

Architect, design, implement, and maintain low-level firmware, middleware, and diagnostic software for PHY chipsets. Develop and troubleshoot embedded C/C++ applications, collaborate with system and hardware designers, and provide leadership in architecture, design patterns, and code quality. Support the full development lifecycle, including pre-silicon co-simulation, laboratory hardware platforms, and silicon bring-up.

Designs and supports semiconductor timing solutions using static timing analysis, physical design principles, timing constraints, signal integrity, clock networks, and timing models. Debugs timing-tool errors, generates reports, analyzes setup and hold timing, and works with large datasets. Collaborates independently with geographically distributed engineering teams, manages multiple assignments, communicates findings clearly, and may supervise others. Requires extensive electrical or computer engineering experience and TCL programming.

Design high-Q FBAR filters and multiplexers for 5G and Wi-Fi RFFE solutions. Own acoustic resonator synthesis, die layout, floor planning, package integration, module co-design, and 3D electromagnetic simulations. Perform yield, Monte Carlo, and corner analyses for high-volume manufacturing. Collaborate with process, modeling, test, module, and design teams to correlate simulations with lab data. Requires advanced RF/microwave expertise and a record of tape-outs or high-volume product releases.