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Lead verification strategy and execute block- and system-level ASIC verification. Define and deploy verification methodologies, build object-oriented environments and testbenches, debug complex issues, and collaborate with design teams to meet coverage, timing, and architectural goals.

Lead top-level ASIC floorplanning and physical design from RTL to tape-out. Own chip floorplanning, partitioning, clock tree delivery, I/O/bump planning, cross-functional integration, vendor/IP evaluation, and methodology improvements.

Design and develop memory compilers and circuit blocks, analyze architectures, simulate designs, and debug silicon issues.

The R&D Engineer IC Design is responsible for the verification of complex switch designs, creating verification environments, executing test plans, and developing testing vectors for silicon diagnostics.

The R&D Engineer will verify complex switch designs, create verification environments using SystemVerilog, execute test plans, and develop ATE testing vectors and C-based diagnostics for silicon testing.

Serve as a bridge between engineering and customers, solving complex issues through innovative solutions, mentoring, and evangelism in the Kubernetes ecosystem.

Develop high-quality software and lead the Mainframe Security and Compliance team. Responsibilities include coding, testing, mentoring, and collaborating with product stakeholders.

The Firmware Engineer will design, develop, debug, and test embedded firmware for networking and storage products, collaborating in a team to support custom firmware features.

The engineer will verify complex switch designs, create verification environments, execute test plans for RTL and gatesim-based designs, and develop testing vectors.

The Senior Manager of U.S. Indirect Tax will provide guidance on software taxation, ensure compliance, manage audits, drive automation, and oversee strategic projects.