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Work as an R&D software engineering intern on Jasper formal verification tools: implement bug fixes and features, write C++ (OOP) on Linux, script flows (Tcl/Python), implement algorithms/data structures, and collaborate on test creation and QA regression.

Supports pre- and post-silicon integration, implementation, verification, timing closure, bringup, and production testing for memory subsystem products such as controllers and PHYs. The role troubleshoots complex customer issues, supports RTL and gate-level simulations, participates in SOC, package, board, and SI/PI reviews, and develops technical documentation. It also applies AI-powered tools and analytics to improve productivity and customer deliverables.

Tracks release schedules, milestones, deliverables, risks, and sign-offs across R&D and Product Verification teams. Maintains release calendars, dashboards, checklists, documentation, and tracking tools such as Jira. Communicates status and blockers across international time zones, records meeting minutes, distributes decisions and action items, and follows up with stakeholders. The role reports to Release Management and supports engineering teams in Taiwan, the United States, and Brazil.

Develop and enhance Cadence SpectreFX FastSPICE and mixed-signal circuit simulation technologies. Responsibilities include collaborating with global engineering teams, analyzing product issues and customer applications, recommending solutions, and proposing implementation plans. The role requires C/C++ development in Unix/Linux, strong data structures and algorithms knowledge, performance optimization, and familiarity with EDA or circuit simulation concepts.

As a Senior Principal Verification Engineer, you will design and support UVM-based verification environments for memory IP models, manage complex verification projects, and integrate tools for robust verification structures.

The role involves bridging R&D and customers, addressing physical design challenges, handling software issues, and innovating design methodologies for chip design.

The Principal Product Engineer will develop innovative characterization solutions for foundational IPs, engage with customers, and drive product adoption efforts.

Lead cross-functional teams to deliver complex services and technology engagements for external customers. Manage project lifecycle, schedules, budgets, risks, resources, and stakeholder communications while collaborating with sales and engineering teams.

Partner with HR, Legal, Finance, Marketing to identify and prioritize back-office improvements; design, prototype, test, and deploy practical solutions (process fixes, automations, AI workflows, agentic systems); work with IT for access and handoff; document logic and assumptions; communicate progress and tradeoffs while prioritizing business impact and maintainability.

Lead deployment of Portable Stimulus methodologies for complex SoC verification. Debug generation/solver and modeling challenges, collaborate with Cadence R&D, develop reference models and best practices, support software-driven verification, reuse across simulation/emulation/post-silicon, and contribute to AI-assisted verification workflows.