Lead Product Engineer: SoC Verification

Posted 3 Days Ago
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Belo Horizonte, Minas Gerais, BRA
In-Office
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Lead deployment of Portable Stimulus methodologies for complex SoC verification. Debug generation/solver and modeling challenges, collaborate with Cadence R&D, develop reference models and best practices, support software-driven verification, reuse across simulation/emulation/post-silicon, and contribute to AI-assisted verification workflows.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Design Systems Inc. is looking for a motivated Lead Product Engineer: SoC Verification to work with us in Belo Horizonte, Brazil for Perspec Team. Perspec is Cadence’s Portable Stimulus solution used by leading semiconductor companies to solve complex SoC and system-level verification challenges.

This role sits at the intersection of verification methodology, system architecture, and EDA product engineering. You will work directly with advanced verification teams at major semiconductor companies to deploy Portable Stimulus (PSS) in real production environments and help drive the evolution of Perspec.

The work spans formal languages, simulation, emulation, virtual platforms, firmware-driven verification, and post-silicon reuse, and increasingly involves AI-assisted verification workflows.

Portable Stimulus is changing how system-level verification is done.

In this role you will work on real verification problems at scale, interacting with some of the most advanced verification teams in the industry and helping shape how hardware/software co-verification is done across simulation, emulation, and silicon. If you enjoy deep technical problem solving, modeling complex systems, and working close to both customers and EDA tool development, this is a unique role.

Cadence has been nominated as a Great Place to Work globally and in Brazil, and is also a Fortune 100 Best Companies to Work For.

 

Job Description:

  • Work directly with semiconductor design and verification teams to deploy Portable Stimulus methodologies in complex SoC programs.

  • Help debug difficult generation and solver issues involving constraints, resources, execution ordering, and scenario realization.

  • Investigate real-world modeling challenges that arise in large system-level PSS environments.

  • Collaborate closely with Cadence R&D to diagnose tool issues, influence new features, and improve PSS standard

  • Help define and refine methodologies for scalable system-level verification.

  • Develop reference models, internal knowledge, and best practices used by both customers and Cadence field teams.

  • Support advanced system-level verification use cases including:

    • software-driven verification

    • device programming flows

    • reuse between simulation, emulation, and post-silicon

    • integration with virtual platforms and firmware environments

  • Contribute to emerging AI-assisted verification flows built around PSS models.

 

Requirements:

  • Complete Bachelor's degree in Computer Science or related areas.

  • Experience in SoC verification, validation, or verification methodology

  • Strong hands-on experience with SystemVerilog and UVM or embedded / bare metal environments

  • Solid understanding of constrained-random verification and system-level test generation

  • Experience debugging complex verification environments

  • Strong programming or scripting skills (C/C++/Python or similar)

  • Ability to work directly with engineering teams to solve difficult technical problems

 

Nice to Have:

  • Exposure to Portable Stimulus (PSS) or interest in learning it

  • Experience with Perspec or other PSS tools

  • Experience working with complex SoC subsystems and protocols such as PCIe, DDR, networking, or ARM-based SoCs

  • Experience with embedded software programming and bare-metal environments

  • Familiarity with emulation, virtual platforms, or post-silicon validation

  • Experience developing verification methodology or reusable verification libraries

 

Additional Job Details:
  • Employment category: CLT.

  • Employment term: 40 hours/week.

  • Competitive benefits.

  • Location: Av Contorno 5800, Belo Horizonte, Minas Gerais, Brazil.

Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments.

For more information, access http://www.cadence.com

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • Bachelor's degree in Computer Science or related field
  • Experience in SoC verification, validation, or verification methodology
  • Strong hands-on experience with SystemVerilog and UVM or embedded / bare metal environments
  • Solid understanding of constrained-random verification and system-level test generation
  • Experience debugging complex verification environments
  • Strong programming or scripting skills (C/C++/Python or similar)
  • Ability to work directly with engineering teams to solve difficult technical problems
  • Exposure to Portable Stimulus (PSS) or interest in learning it
  • Experience with Perspec or other PSS tools
  • Experience with complex SoC subsystems and protocols such as PCIe, DDR, networking, or ARM-based SoCs
  • Familiarity with emulation, virtual platforms, or post-silicon validation
  • Experience developing verification methodology or reusable verification libraries

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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