Principal Product Engineer - Memory IP

Posted 12 Days Ago
Be an Early Applicant
2 Locations
In-Office
Senior level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
Supports pre- and post-silicon integration, implementation, verification, timing closure, bringup, and production testing for memory subsystem products such as controllers and PHYs. The role troubleshoots complex customer issues, supports RTL and gate-level simulations, participates in SOC, package, board, and SI/PI reviews, and develops technical documentation. It also applies AI-powered tools and analytics to improve productivity and customer deliverables.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

 Primary Responsibilities:
○ Supporting pre-silicon integration, usage, and implementation of memory subsystem products
○ Helping with internal system integration and QA testing of memory subsystem products (Controller + PHY)
Analyzing and resolving complex subsystem application or implementation issues and providing
professional guidance to customers
○ Supporting various memory PHY and controller SOC integration reviews and implementation reviews
○ Assisting customers with RTL and gate-level simulations to verify functionality
○ Assisting customers with timing closure and other aspects of physical integration
Participating in development and refinement of product documentation and checklists for customer
applications
○ Supporting post-silicon bringup and production test activities for customers as needed
Enhancing customer experience by providing prompt, thorough, and technically accurate responses to
customer questions
○ Leveraging AI-powered tools and assistants to enhance productivity, improve decision making, and maintain
high-quality customer deliverables.
○Applying AI-powered analytics tools to extract insights, identify patterns, and generate actionable
recommendations from complex datasets
Position Requirements:
○ B.S Electrical/Computer Engineering (or similar degree) and 7+ years of overall experience -OR- M.S
Electrical/Computer Engineering (or similar degree) and 5+ years of overall experience
○ Experience working with DDR5/4/3, LPDDR5/4/3, HBM3, GDDR6 or similar IPs
○ Verilog RTL design and gate level verification experience
○ Synthesis and static timing analysis experience (physical implementation/verification experience is a plus)
○ Familiarity with industry standard DFT flows and test methodologies.
○ Familiarity with package and board design
○ Ability to read schematics and participate in SI/PI reviews for customer board/package implementation
Preferred Qualifications
○ Experience with Memory PHY and DSP based architecture
○ Experience with embedded microcontroller FW
○ Background with scripting and applying AI solutions to daily workflows

 

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or similar, plus 7 or more years of overall experience
  • Master's degree in Electrical Engineering, Computer Engineering, or similar, plus 5 or more years of overall experience
  • Experience with DDR5, DDR4, DDR3, LPDDR5, LPDDR4, LPDDR3, HBM3, GDDR6, or similar memory IPs
  • Verilog RTL design and gate-level verification experience
  • Synthesis and static timing analysis experience
  • Familiarity with industry-standard DFT flows and test methodologies
  • Familiarity with package and board design
  • Ability to read schematics and participate in signal integrity and power integrity reviews
  • Experience with memory PHY and DSP-based architecture
  • Experience with embedded microcontroller firmware
  • Background in scripting and applying AI solutions to daily workflows
  • Physical implementation and verification experience

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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