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Drive development and customer adoption of advanced backend custom IC design flows in Cadence Virtuoso for advanced nodes. Provide customer-facing support: troubleshoot issues, create automation and scripts, collaborate with R&D, and deliver documentation and training to enable efficient layout and signoff flows.

You will design and implement high-performance software while applying machine learning techniques to complex problems in electronic design automation.

Embed with strategic semiconductor customers to deploy LLM- and agent-based AI into end-to-end EDA flows (RTL through signoff). Architect agentic workflows, integrate Cadence AI products, define KPIs for productivity and ROI, guide secure LLM access and infrastructure, run design reviews, and produce reusable playbooks to scale deployments across sites.

Design and develop analog/mixed-signal IC blocks for high-speed SerDes from concept through verification. Responsibilities include circuit design (drivers, receivers, serializers/deserializers, PLLs, ADC/DACs, biasing, regulators), simulation and layout using CAD tools, lab testing, and collaboration with cross-functional teams.

Prepare quarter-end reporting and audit committee deliverables, validate finance data from SAP/Incorta/CPM/NGA, generate reports and ad hoc analyses, perform data quality reviews and reclasses, support UAT and system enhancements, assist acquisition integrations, and partner with quote-to-cash and cross-functional teams to resolve reporting discrepancies.

Lead design and implementation of the SystemVerilog compiler and code generator for Xcelium, optimize front-end and codegen for multi-billion gate designs, perform performance engineering in C++, and prototype innovations like LLM-enhanced, parallel, and distributed compilation.

The Business Systems Analyst will enhance Salesforce and related systems, optimizing workflows and identifying automation opportunities in a global environment, while collaborating across teams to ensure robust solutions.

The role involves designing and testing mixed-signal circuits, contributing to project leadership, and collaborating with the digital team on functional closure.

Develop and debug bare-metal C firmware for DDR5 PHY on microcontrollers, collaborate with hardware designers and verification teams to implement training algorithms, perform RTL and silicon bring-up debugging, and use scripting and EDA tools for co-verification and simulation.

Design-for-Test (DFT) engineer responsible for scan chain and compression insertion, MBIST/LBIST, ATPG pattern generation and verification, debugging failures, verifying ATPG testbenches, and collaborating across architecture, design, and customer teams. Work with JTAG/IEEE test standards and Cadence flows to meet test coverage and quality metrics.