Top Tech Jobs & Startup Jobs

Lead verification for GPU/SoC display IP: define verification scope and testplans, build UVM-based infrastructure, develop UVM and C/C++ testbenches, drive coverage closure, debug silicon integrations, and collaborate with architects, partners, and customers globally.

Design and implement idiomatic, safe Rust libraries and APIs for CUDA GPU computing; build Rust abstractions over native C/C++ interfaces; develop and maintain supporting C/C++ components; ensure FFI and Python interoperability; optimize cross-language and GPU performance; own features end-to-end including testing, profiling, benchmarking, documentation, packaging, and maintenance; collaborate with compiler, runtime, and Python teams; investigate and resolve safety, correctness, compatibility, and performance issues.

Serve as technical lead between NVIDIA and hyperscale CSPs on GPU firmware and system software. Drive firmware update orchestration, recovery procedures, multi-GPU coordination, telemetry/health monitoring, and incorporate CSP feedback into NVIDIAs roadmap to improve fleet-scale manageability and reliability.

Lead end-to-end release management for Compute Platform Software: coordinate cross-team release activities, manage branching/version control, assess release readiness and risk, build automation and dashboards, define KPIs and schedules, work with engineering/QA/product/operations, drive post-release validation and continuous process improvements.

Lead developer relations for CAE by building technical expertise, integrating NVIDIA software stacks into partner projects, supporting onboarding with code samples and demos, monitoring ecosystem trends, and collaborating with partners and internal teams to drive adoption of NVIDIA AI and accelerated computing technologies.

Drive physical design of high-frequency, low-power CPUs/GPUs/SoCs at block, cluster, or full-chip level with emphasis on netlist quality: equivalence checking/formal verification, CDC and MTBF analysis, logic synthesis, timing convergence, STA, constraint generation/management, and ECO implementation. Use industry-standard EDA tools and scripting to debug and improve flows.

Lead technical engagements with cloud service providers on rack-scale system software and firmware. Drive architecture alignment, integration readiness, error handling and recovery, health telemetry, firmware orchestration, and serviceability. Capture CSP feedback, influence NVIDIA system software design, improve tooling and tests, and mitigate execution risks through early collaboration.

Lead technical engagement with OEM/ODM ecosystem partners to enable MGX-based high-performance hardware. Provide system-level electrical, mechanical, and thermal engineering expertise; drive integration of compute, networking, power, cooling, and mechanical subsystems; define validation strategies; lead product reviews and readiness assessments; deliver partner training and onboarding; collaborate across product, engineering, operations, manufacturing, and business teams to grow the MGX hardware ecosystem.

Apply LLMs, agentic systems, and reinforcement learning to front-end ASIC problems (RTL generation, verification, PPA). Build data generation, evaluation, and production ML tooling; integrate coding agents into EDA/validation flows; collaborate with model teams to fine-tune domain-specific models and deliver measurable speedups to ASIC schedules.

Lead DFT/DFX architecture and methodologies across products, implementing test access, IO/memory BIST, scan compression, and high-speed test architectures. Define/prototype in-system test and ISO26262 diagnostics, support silicon debug and ATE bring-up, collaborate with cross-functional teams to productize test flows and tools, and mentor junior engineers on test designs and trade-offs.