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Responsible for front end design and verification of ASIC design blocks, including architecture definition, logic design, synthesis, and verification through simulation and analysis of timing.

Develops and deploys semiconductor timing sign-off flows using Python, Perl, Tcl, and Unix shell. Responsibilities include EDA flow development for PrimeTime, Tempus, Innovus, and RedHawk; automation; statistical data analysis and modeling; and support for chip design teams. The role requires advanced digital IC design expertise, strong communication, multitasking, problem-solving, and collaboration across projects.

Develop and deploy advanced timing sign-off methodologies for SOC, 3D/2.5D IC, and multi-die designs. Lead EDA flow development using Primetime, Tempus, and Innovus, while applying statistical analysis, silicon technology, testability, and yield expertise. The role requires extensive tapeout and timing sign-off experience, scripting and automation skills, cross-functional collaboration, and autonomous problem solving in a fast-paced engineering environment.

Lead facet coating process integration for optoelectronic lasers and detectors. Develop and scale multilayer IBS/ALD coatings, run DOE/SPC/FMEA, perform metrology (ellipsometry, AFM, spectrophotometry), drive CAPA/root-cause analyses, manage equipment lifecycle and subcontractor performance, implement KPIs/dashboards, and collaborate with Product, Quality, and R&D to improve yield, reliability, and production efficiency in a 24/7 manufacturing environment.

Design and validate high-power system enclosures and liquid cooling infrastructure across the hardware development lifecycle. Lead thermo-mechanical lab operations, thermal testing, simulation correlation, component validation, troubleshooting, and vendor collaboration. Design rack-mount systems, manage thermal solution suppliers, support compliance and reliability testing, and resolve thermal issues in high-power prototypes. Collaborate with electrical, manufacturing, compliance, and contract manufacturing teams to bring products from concept through volume production.

Designs system-level simulation methodologies and verifies transmitter full-chain performance for RF front-end modules. Integrates power amplifiers, switches, filters, and PCBs; automates simulation workflows; debugs system issues; and correlates simulation results with laboratory measurements. The role requires RFIC circuit design expertise, transceiver architecture knowledge, and proficiency with ADS, Cadence Virtuoso, Dynamic Link, Golden Gate, HFSS, and AI coding tools.

Lead the design, development, and deployment of automated RF and mixed-signal test solutions using C# and TestStand on PXI-based automated test equipment. Responsibilities include RF test development, system integration, hardware and software debugging, design-for-test feedback, mentoring junior engineers, and improving reusable, scalable test architectures throughout the NPI lifecycle.

Design and optimize analog and mixed-signal IC blocks from behavioral models through transistor-level implementation, layout, verification, characterization, and production test. Lead analog engineering projects, define analog-digital interfaces, review package routing and test boards, analyze noise, distortion, power, and linearity, and debug silicon performance. Collaborate with layout, package, digital, and automatic test engineering teams while documenting circuit operation and performance.

Drive quality and reliability strategy for silicon photonics products, manage device and transceiver qualification, lead failure analyses, and implement corrective actions. Partner with design and manufacturing teams on reliability testing, product and process qualifications, change management, transfers, and volume ramps. Prepare customer-facing quality reports, support audits, and develop statistical analysis and database infrastructure for high-volume manufacturing. Travel may be required up to 10%.

Design and deliver high-quality SystemVerilog RTL for advanced process nodes (5nm and below), optimize PPA, perform CDC/RDC analysis and low-power techniques, drive timing closure and hand off to physical design, and collaborate with Architecture, Verification, and Physical Design teams.