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2 Days AgoSaved
In-Office
5 Locations
98K-157K Annually
Senior level
98K-157K Annually
Senior level
Semiconductor
The IT Compliance Engineer manages compliance programs, supports audits, mitigates risks, collaborates with teams, and ensures regulatory adherence.
Top Skills: Cloud PlatformsDevOpsGrc ToolsIsoNistSoc
2 Days AgoSaved
In-Office
San Jose, CA, USA
120K-192K Annually
Senior level
120K-192K Annually
Senior level
Semiconductor
This role involves executing Physical Design tasks, managing RTL to silicon tape-out processes, and collaborating with IC Design RTL Engineers in a data center context.
Top Skills: Eda ToolsPerlTcl
2 Days AgoSaved
In-Office
San Jose, CA, USA
141K-226K Annually
Expert/Leader
141K-226K Annually
Expert/Leader
Semiconductor
The role involves executing Physical Design, Synthesis, Physical Verification, and Timing Closure for IC design while collaborating with RTL engineers and managing the design process from RTL to tape-out.
Top Skills: Eda ToolsPerlTcl
2 Days AgoSaved
In-Office
San Jose, CA, USA
120K-192K Annually
Senior level
120K-192K Annually
Senior level
Semiconductor
The Physical IC Design Engineer will manage Physical Design tasks, timing closure, and collaborate with RTL Engineers, focusing on the full cycle from RTL to silicon tape-out.
Top Skills: Eda ToolsPerlTcl
2 Days AgoSaved
In-Office
San Jose, CA, USA
120K-192K Annually
Senior level
120K-192K Annually
Senior level
Semiconductor
As a Physical IC Design Engineer, you'll execute physical design, timing closure, floor-planning, and collaborate with RTL engineers on complex IC designs.
Top Skills: Eda ToolsPerlTcl
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2 Days AgoSaved
In-Office
San Jose, CA, USA
141K-226K Annually
Expert/Leader
141K-226K Annually
Expert/Leader
Semiconductor
The DFT IC Design Engineer will implement and verify DFT aspects in IC design and collaborate with engineering teams on related methodologies.
Top Skills: AteAtpgBisrBistDftMbistNetlistsRtlScanSiemens Tessent Tool
2 Days AgoSaved
In-Office
San Jose, CA, USA
141K-226K Annually
Senior level
141K-226K Annually
Senior level
Semiconductor
The Physical IC Design Engineer will execute physical design tasks, including timing closure, floor-planning, and collaboration with RTL engineers, utilizing TCL/PERL scripting and EDA tools.
Top Skills: Eda ToolsPerlTcl
2 Days AgoSaved
In-Office
San Jose, CA, USA
120K-192K Annually
Senior level
120K-192K Annually
Senior level
Semiconductor
The Physical IC Design Engineer will execute Physical Design, Synthesis, Verification, and Timing Closure while collaborating with RTL Engineers in a data center solutions context.
Top Skills: Eda ToolsPerlTcl
2 Days AgoSaved
In-Office or Remote
Location, WV, USA
152K-243K Annually
Expert/Leader
152K-243K Annually
Expert/Leader
Semiconductor
The Solutions Architect drives sales, resolves technical issues, and fosters customer relationships while guiding strategic IT transformations and solution adoption.
Top Skills: Ca Technologies SolutionsEnterprise Software
2 Days AgoSaved
In-Office
4 Locations
107K-190K Annually
Senior level
107K-190K Annually
Senior level
Semiconductor
The Product Marketing Specialist will lead tool strategy and design, engage with customers and stakeholders, and collaborate cross-functionally to meet business needs.
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