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Lead DFT programs including specification, implementation, and verification for ASIC products, focusing on various phases of SoC DFT-related activities and customer interactions.

The Layout Engineer will develop and verify layouts for high-speed analog and mixed-signal circuits, focusing on power optimization and performance within state-of-the-art integrated circuits.

The Logic Design Engineer will design and verify high-performance Ethernet switch ASICs, including RTL implementation, verification, and debug analysis, while collaborating with the program lifecycle.

The IC Design Engineer will implement mixed-signal ASICs for consumer and satellite projects, involving physical design, verification, and collaboration with various teams. A focus on low-power technologies and extensive tool experience is essential.

As a Metrology Engineer, you will develop metrology recipes, build test fixtures, recommend process improvements, and conduct statistical analysis to improve product yield and quality.

As a PHY Application Engineer, you will support customers on Ethernet PHY products, providing pre-sales and post-sales assistance while addressing complex technical issues and ensuring successful product launches.

Design and implement analog/mixed-signal circuits, develop test plans, support internal and external customers, and lead project management efforts.

The Verification Engineer will work on IPs for ASIC products, focusing on verification of subsystems and ensuring design integrity through methodologies like UVM and System Verilog.

As a Physical IC Design Engineer, you'll execute physical design, timing closure, floor-planning, and collaborate with RTL engineers on complex IC designs.

The Physical IC Design Engineer will execute Physical Design, Synthesis, Verification, and Timing Closure while collaborating with RTL Engineers in a data center solutions context.