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The Silicon Photonics PIC Design Engineer will design, simulate, layout, test, and verify silicon photonics components and circuits, collaborating with cross-functional teams and utilizing advanced simulation tools.

The Engineering Program Manager will lead the delivery of complex storage, PCIe switching, and Ethernet NIC solutions, focusing on program planning, budget management, and customer requirements while ensuring quality and timely delivery of Broadcom solutions. The role involves managing multiple projects, collaborating with internal teams, and applying process improvements across departments.

The role involves developing silicon products for datacenters and AI/ML platforms. Responsibilities include logic synthesis, physical design, power optimization, and timing analysis with a focus on high-speed chip implementations in 5nm/3nm technology.

This role involves designing and validating chips for high-speed optical communication products, including block-level design, RTL coding, simulations, and silicon validation. The engineer will work on design specifications, perform design tradeoff analysis, and support silicon bring-up processes, while coordinating with cross-functional teams.

The Physical Design Engineer will lead ASIC implementation projects involving synthesis, physical design, timing closure, and validation. They will work with design teams to implement complex designs, ensure quality through peer reviews, and adapt to changing project requirements.

The Memory Design Engineer will be involved in developing memory compilers and custom macros, analyzing memory architectures, designing circuit blocks, simulating circuit designs, performing layout extraction, and debugging silicon issues while documenting specifications and working on characterization flows.

The ASIC Digital Physical Design Engineer is responsible for physical design processes including synthesis, floor-planning, clock constraints, and power analysis. They must have extensive experience in verification methodologies, design tape-out processes, and familiarity with industry-standard tools like Cadence. The role requires strong knowledge of high-speed design environments, especially relating to TSMC technology.