Physical Design Engineer

Reposted 2 Days Ago
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San Jose, CA, USA
In-Office
141K-226K Annually
Expert/Leader
Software • Semiconductor • Manufacturing
The Role
The Design Implementation Engineer will manage design implementation for ASIC/SoC, focusing on timing closure, physical verification, and adopting Broadcom's design methodologies. Expected to utilize tools for timing analysis, power optimization, and equivalent checks.
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Job Description:

Broadcom is searching for an ASIC top level floorplan Physical Design Engineer to join the Asic Products Division. This position involves working with the latest technology to continue driving next generation Artificial Intelligence and PCIe Switch Products. More specifically, this position will require in-depth knowledge and expertise in all Physical Design aspects of taking RTL to silicon tapeout.

Responsibilities:

  • Own chip floor planning, partition creation, clock tree and delivery of top level partitions

  • Resolve physical design issues related to chip integration and assembly

  • Manage all cross functional interactions related to top level floorplanning, I/O and bump planning with package team

  • Develop and improve floorplan methodologies using both industry and  internal tools

  • Perform technical evaluations of IPs, providing recommendations and assessments to meet design specification

Preferred qualifications:

  • Bachelors and 12+ years of experience in top level floorplanning  with a focus on die size estimate, partitioning, clocking and pin assignment, or

  • Master's degree in Electrical Engineering and 10+ years of experience in top level floorplanning  with a focus on die size estimate, partitioning, clocking and pin assignment

  • Experience working on various technologies (Switch Fabric, Arbiter, High Speed DDR, SerDes, HBM, D2D I/O, chiplet etc)

  • Experience in resolving chip level DRC/LVS/EMIR issues for advance nodes and tape out experience

  • Proven track record with bump planning, RDL routes and multi voltage domain designs 

  • Experience with hierarchical design planning, power grid design, structured clocks, top level pipeline placement, custom routes and bump planning

  • Experience in collaborating with design, package and methodology teams during development phase

  • Experience in scripting languages like  Python, Tcl, or Perl

  • Must work in person at our San Jose site and no remote work allowed

Additional Job Description:

Compensation and Benefits

The annual base salary range for this position is $141,300 - $226,000

 

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Skills Required

  • Expertise in place and route and/or timing (constraints, STA)
  • Proficiency in design implementation activities at block and SoC level
  • Experience in floor-planning, partitioning, placement, clock tree synthesis, and routing
  • Experience with formal verification, timing analysis, and Eco implementation
  • Experience with tools such as Primetime, ICC2, Innovus, Caliber, LEC, PrimeTime
  • Full chip tapeout experience based on 7nm and lower technologies
  • Hands-on experience with timing analysis and place and route tools for ASIC/SoC Design

Broadcom Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Broadcom and has not been reviewed or approved by Broadcom.

  • Equity Value & Accessibility Equity is used broadly through RSUs with quarterly or annual vesting, and an ESPP with a discount and look‑back that can add meaningful upside. Company disclosures show ongoing equity grants, including inducement RSUs tied to acquisitions, underscoring equity’s central role in total rewards.
  • Retirement Support A 401(k) plan with a competitive company match and immediate vesting is consistently highlighted, supporting long‑term savings. Tax‑advantaged accounts like HSA/FSA further strengthen the financial wellness toolkit.
  • Pay Growth & Progression Compensation ceilings in technical tracks are described as high, with wide ranges and very strong totals for experienced engineers. Sales compensation is also characterized as competitive, supporting attractive on‑target earnings.

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The Company
HQ: San Jose, CA
38,985 Employees
Year Founded: 1991

What We Do

Broadcom Inc. (NASDAQ: AVGO) is a global technology leader that designs, develops and supplies semiconductor and infrastructure software solutions.

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