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Design and execute verification plans for IP blocks and systems using SystemVerilog/UVM. Build testbenches, develop Python behavioral models, analyze simulations, debug failures, maintain automation/regression frameworks, and collaborate with design and architecture teams to improve verification methodologies and resolve root causes.

Perform SI/PI analysis and mask-based timing signoff for parallel interfaces across IC, package, and PCB (including 2.5D/3D/MCM). Tasks include EM extraction and modeling, PDN AC/transient analysis, IO channel and pre-layout transceiver modeling, automation of sign-off flows, working with EDA vendors, and producing reports/presentations for customers and internal teams.

Lead constrained-random verification of high-throughput Ethernet ASICs for AI/ML acceleration using SystemVerilog/UVM testbenches, drive coverage closure, run simulations with VCS/Incisive, script automation, collaborate with global design and architecture teams, and provide technical leadership.

Develop and implement complex ASIC verification environments and test plans for high-performance network switch ASICs/FPGAs. Collaborate with architects and design teams, perform simulations, and drive verification to closure through tape-out and production-ready delivery.

Drive revenue and growth for existing enterprise customers across Broadcom Software portfolio. Manage pipeline, build senior-level relationships, create account and territory plans, qualify and close deals, prepare proposals, negotiate, and exceed quarterly and annual sales targets.

Drive revenue growth for assigned enterprise accounts across Broadcom Software (VMware, CA, Symantec). Manage deal pipeline, build senior relationships, create account plans, negotiate and close deals, and exceed quarterly and annual sales targets.

The Senior Software Engineer will design and implement scalable distributed storage solutions, ensure reliability, manage Kubernetes workloads, and lead product feature delivery.

The Fab Manufacturing Quality Engineer will enhance quality systems in semiconductor manufacturing, lead meetings, and develop data mining tools while managing quality processes and improvement initiatives across teams.

Lead design and implementation of an AI Virtualization Stack for ESXi, integrating PyTorch/JAX backends via OpenXLA. Optimize ML acceleration (LLM inference, KV-caching, FlashAttention), troubleshoot GPU/XPU runtime issues, collaborate with driver/device teams and vendors, and deliver production-quality code and documentation.

The Senior Product Owner leads product development for Mainframe solutions at Broadcom, collaborating with cross-functional teams to deliver features based on customer needs and product roadmaps.