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Leads custom analog layout and verification for high-speed SerDes and memory I/O circuits in advanced semiconductor nodes. Collaborates with design teams on circuit implementation, supports IP and chip-level integration, assists with customer requirements and IP delivery, and applies high-speed layout techniques involving matching, parasitic minimization, power grids, ESD, EM, and IR-drop analysis.

Own the SoC and product specification stack for a 1.6T retimer SoC and AEC products operating at 224G/lane PAM4. Author normative, traceable specifications for RTL, firmware, software, SI/PI, manufacturing, qualification, and customer engineering teams. Represent architecture in hyperscaler and strategic customer negotiations, covering qualification testing, FEC telemetry, CMIS vendor pages, and thermal commitments.

The DFT Engineer will implement hierarchical MBIST, scan, boundary scan, and IJTAG methodologies; generate ATPG patterns; analyze fault coverage; perform timing simulations; define test-mode constraints; debug silicon issues; and collaborate with test and production engineering teams during device probe and final-test bring-up. The role requires strong debugging, scripting, communication, and semiconductor design-for-test experience.

Design, model, verify, and integrate custom high-speed analog circuits for SerDes transceivers in advanced semiconductor technologies. Responsibilities include analog IP and chip-level integration, circuit simulation, layout verification, customer support, silicon collaboration, and design status reporting. The role focuses on circuits such as equalizers, clock generators, PLLs, DLLs, CDRs, ADCs, DACs, amplifiers, buffers, regulators, filters, serializers, and output drivers.