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Manage and support integrated analog and digital EDA environments, develop and automate CAD flows, support PDK installation and qualification, troubleshoot tools, guide design teams, manage EDA vendors, and improve design productivity. The role requires expertise across analog, digital, mixed-signal IC design, physical verification, parasitic extraction, implementation, advanced technology nodes, licensing, revision control, release management, and multi-project data management.

Leads hands-on development and delivery of real-time embedded firmware for high-speed AEC retimer silicon. Responsibilities include C/C++ coding, state machines, drivers, SerDes adaptation, hardware and silicon bring-up, debugging, testing, CI, and cross-functional coordination. The role mentors engineers, establishes coding standards, manages work packages, and supports pre-silicon through production development across RISC-V or ARM platforms.

Architect and lead CMIS software stacks, host interoperability testing, manufacturing test orchestration, telemetry pipelines, customer SDKs, and developer tools. Ensure compliance with CMIS, OSFP, SFF-8024, OIF, and related standards. Responsibilities include regression testing with hyperscalers, ATE integration, yield analytics, firmware-to-cloud telemetry, release management, architecture documentation, and customer, manufacturing, and standards engagement. Travel up to 25% is required.

Design and verify high-speed digital circuits for serial transceivers, DDR, and memory interfaces. Responsibilities include RTL design, analog-digital interface specification, synthesis, timing analysis, verification, chip integration, protocol analysis, and post-silicon lab bring-up. The engineer will collaborate with analog, verification, physical implementation, and customer teams while supporting requirements, debugging, characterization, and product delivery.

Leads custom analog layout and verification for high-speed SerDes and memory I/O circuits in advanced semiconductor nodes. Collaborates with design teams on circuit implementation, supports IP and chip-level integration, assists with customer requirements and IP delivery, and applies high-speed layout techniques involving matching, parasitic minimization, power grids, ESD, EM, and IR-drop analysis.

The DFT Engineer will implement hierarchical MBIST, scan, boundary scan, and IJTAG methodologies; generate ATPG patterns; analyze fault coverage; perform timing simulations; define test-mode constraints; debug silicon issues; and collaborate with test and production engineering teams during device probe and final-test bring-up. The role requires strong debugging, scripting, communication, and semiconductor design-for-test experience.

Design, model, verify, and integrate custom high-speed analog circuits for SerDes transceivers in advanced semiconductor technologies. Responsibilities include analog IP and chip-level integration, circuit simulation, layout verification, customer support, silicon collaboration, and design status reporting. The role focuses on circuits such as equalizers, clock generators, PLLs, DLLs, CDRs, ADCs, DACs, amplifiers, buffers, regulators, filters, serializers, and output drivers.