Challenges are our drive, innovation our calling. We at Kandou are a team of passionate accomplished professionals making a mark in the semiconductor industry. We're an innovative leader in high-speed and energy efficient chip-chip link solutions critical to the evolution of the electronics industry, continuously developing to meet the demands of not just the customers of today, but of tomorrow too. If you love to be part of a high-tech scale-up and are motivated by pushing your limits and challenging the status quo, we have an opportunity for you.
We are actively seeking a resourceful DFT Engineer based in Lausanne, Switzerland or UK
Key Responsibilities:
Hierarchical MBIST and scan insertion, BSD implementation
ATPG pattern generation, coverage analysis, converging to high coverage metrics
Pattern simulations with timing
Defining test mode timing constraints, analyzing the timing reports and converge timing
Developing cycle accurate functional patterns using IJTAG methodology
Closely working with the test and production engineering teams to debug and bring up devices at probe and final test
Debugging silicon issues
Skills:
Excellent communication skills, and strong team player with can do type of attitude
Excellent debugging skills
Good scripting skills to develop automation
Qualifications:
5+ years of DFT experience including implementation, test pattern development, and simulation
Proven experience in contributing to DFT solution to complex designs
Experience working with IJTAG methodologies
Experience with hierarchical MBIST insertion, hierarchical scan insertion and scan compression methodologies
Experience in ATPG pattern generation for different kinds of fault models, fault coverage analysis and converging to high coverage metrics
Good debug capabilities in simulating patterns with timing
Experience with industry standard EDA tools for DFT, timing, and simulation
Knowledge of System Verilog
Education:
Bachelor of Engineering in Electronics and Electrical Engineering, Computer Engineering (equivalent or higher)
Skills Required
- 5+ years of DFT experience, including implementation, test pattern development, and simulation
- Experience contributing DFT solutions for complex designs
- Experience with IJTAG methodologies
- Experience with hierarchical MBIST insertion
- Experience with hierarchical scan insertion and scan compression methodologies
- Experience generating ATPG patterns for different fault models
- Experience with fault coverage analysis and convergence to high coverage metrics
- Good debugging capabilities in simulating patterns with timing
- Experience with industry-standard EDA tools for DFT, timing, and simulation
- Knowledge of SystemVerilog
- Bachelor of Engineering in Electronics and Electrical Engineering, Computer Engineering, or equivalent/higher
- Excellent communication skills and ability to work as a strong team player
- Excellent debugging skills
- Good scripting skills for developing automation
What We Do
Kandou AI is a fabless semiconductor company developing high-speed connectivity for AI infrastructure. Its patented Copper MIMO, also known as Chord Signaling, sends correlated signals at data-processing speeds of 448 Gbps and beyond, providing an alternative to optical interconnects. The company’s technology targets AI data-movement bottlenecks and memory-wall constraints, while its platforms emphasize improved efficiency, lower power and cost, and scalability.
