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Lead the design and integration of memory controller IPs, focusing on DDR and LPDDR technologies, performance optimization, and providing mentorship to junior engineers.

The STA Methodology Lead will develop and support static timing analysis flows, collaborate on methodology improvements, and interface with CAD/DA teams to ensure flow robustness, with strong scripting skills necessary.

As a Silicon Design Engineer, you will drive power analysis and optimization for FPGA products, collaborating with various teams and defining power analysis flows.

The Sales Applications Engineer will drive FPGA technology adoption, work with customers to define product requirements, and provide technical support and training.

As an EMIR Technical Lead, you will lead power/EMIR methodology signoff, collaborate with teams to optimize designs, and develop automation flows, mentoring junior engineers in the process.

As a Physical Design Engineer, you will execute design tasks from netlist to GDSII, optimize PPA, and collaborate with various teams for FPGA/SoC implementations.

As Lead DV Engineer, you'll validate Altera's IPs, develop test plans, create testbenches, and collaborate on hardware testing to ensure quality and functionality.

The role involves developing applications for a Cyber Security processor engine, focusing on packet inspection, traffic analysis, and optimizing high-performance software systems.

The role involves overseeing and designing the enterprise-wide PLM architect, focusing on system integration and data migration, ensuring it meets business objectives and fosters innovation.

The Product Development Engineer will develop DFT strategies for FPGAs, collaborate on testability, and optimize manufacturing test processes while analyzing test data and driving improvements.