Top Tech Jobs & Startup Jobs

Define and drive Altera's security positioning across design, data, and supply chain security. Create external technical messaging, assets, and sales enablement; articulate value of FPGA-based crypto agility, SDM/root of trust, and PQC strategies. Analyze competitors, identify trends, and launch campaigns aligned to regulatory shifts to position Altera as a trusted security platform.

Consult on and optimize Workday Recruiting and Learning processes globally: streamline workflows, increase recruiter efficiency, improve onboarding and learning administration, build dashboards and analytics, identify automation/AI opportunities, and partner with HR, TA, and business leaders to implement scalable Workday solutions and a long-term optimization roadmap.

Design, implement, and optimize FPGA placement algorithms to improve timing, congestion, resource utilization, and runtime for large designs. Integrate placement into the compiler flow, collaborate with routing, synthesis, architecture, and timing teams, analyze convergence and QoR, and validate toolchain performance across diverse workloads.

Architect, implement, and optimize FPGA-based signal processing and embedded computing solutions for aerospace and defense. Work with customers and internal teams to deploy DSP, communications, and AI algorithms on FPGA devices; develop benchmarks, reference designs, and documentation; analyze and tune system performance for throughput, latency, power, and resource utilization; support debugging, performance tuning, and technical enablement.

Own and reconcile fixed asset and related general ledger accounts (PPE, CIP/AUC, prepaids, AP, accruals). Prepare roll-forwards, journal entries, physical count coordination, capitalization reviews, SOX controls support, audits, and ERP/fixed-asset process improvements.

Manage monthly close and GL for prepaids, AP, accruals, liabilities, and PPE. Lead reconciliations, journal entries, roll-forwards, variance analysis, SOX controls, and audit support. Review IT/R&D contracts for accounting treatment, improve processes and systems, and coordinate U.S. and international accounting teams.

Perform block-level physical implementation of custom IP and SoC designs from RTL to GDSII. Execute synthesis, floorplanning, P&R, CTS, STA, and physical verification. Resolve timing, power, and signal-integrity issues, support DFT integration and signoff, and develop/automate physical design methodologies to optimize PPA and manufacturability.

Lead physical implementation and STA for advanced FPGA SoCs from floorplanning through final timing closure. Drive block- and SoC-level implementation, develop SDC/UPF constraints, perform MMMC STA with PrimeTime, resolve timing/physical violations, execute signoff/physical verification, build Tcl/Python automation and evaluate ML/AI-assisted flows, and mentor engineers while coordinating with RTL, CAD, library, and packaging teams.

Lead architecture, microarchitecture, RTL design, and technical direction for scalable Network-on-Chip IPs for FPGA platforms. Develop RTL, prototypes, simulation models, and software bring-up; optimize for power, performance, area, and reliability. Guide verification, collaborate with cross-functional teams, mentor engineers, and apply EDA and AI-enabled automation to meet project schedules and quality goals.

Lead thermal and thermomechanical characterization and qualification of advanced 2.5D/3D semiconductor packages. Develop and calibrate FEA models, define and run warpage/coplanarity/reliability tests, perform lifetime prediction and failure analysis, own DFMEA activities, and produce customer reports on package reliability.