Top Tech Jobs & Startup Jobs

Designs and improves security across Azure and AWS environments, including cloud architecture, IAM, networking, workloads, infrastructure as code, automation, monitoring, detection, incident response, vulnerability management, and governance. The role establishes guardrails and secure standards, embeds controls into CI/CD, investigates cloud security events, supports compliance, and mentors engineers while partnering with platform, infrastructure, application, identity, and security operations teams.

Leads enterprise network security strategy, architecture, and roadmap across on-premises, cloud, data center, laboratory, campus, WAN, and hybrid environments. Designs Zero Trust, segmentation, firewall, ZTNA, SASE, SD-WAN, detection, telemetry, and automation solutions. Provides senior incident-response expertise, conducts architecture and risk assessments, supports audits, establishes standards and governance, and mentors engineers while advising technical and executive stakeholders.

Design, implement, verify, and optimize synthesizable RTL for FPGA and programmable hardware solutions supporting AI acceleration and Physical AI applications. Develop microarchitectures, datapaths, control logic, and accelerator architectures; support synthesis, timing closure, debugging, hardware-software integration, and system bring-up. Collaborate with architecture, verification, firmware, software, and physical design teams to deliver high-performance, scalable computing solutions for robotics, autonomous systems, machine vision, and edge AI.

Leads annual planning, forecasting, long-range financial planning, financial modeling, variance analysis, executive reporting, investment evaluation, and performance management. Partners with senior leadership and cross-functional teams to guide strategic decisions, resource allocation, IPO readiness, and financial process improvements. Supports board and investor presentations while improving reporting frameworks and forecast accuracy.

Provides hands-on technical leadership for RTL architecture, microarchitecture, implementation, integration, verification, and delivery of FPGA and programmable SoC subsystems. Leads high-performance datapath, memory, interconnect, packet-processing, and acceleration designs while balancing power, area, timing, reliability, and schedule. Establishes RTL methodologies, drives cross-functional technical execution, resolves complex design issues, and mentors engineers across global teams.

Lead architecture, microarchitecture, RTL development, integration, verification support, timing closure, bring-up, and performance characterization for FPGA and programmable SoC subsystems. Translate system requirements into scalable digital designs, drive tradeoffs across performance, power, area, and reliability, and resolve complex cross-functional issues. Establish reusable IP, coding standards, automation, and quality practices while mentoring engineers and influencing technical roadmaps across global hardware, software, verification, and product teams.

Leads functional safety architecture for semiconductor and IP development across avionics, automotive, defense, space, and industrial markets. Defines safety concepts, mechanisms, requirements, and architectures; performs FMEA, FMEDA, FTA, and DFA analyses; guides ASIL/SIL decomposition and verification strategies; and ensures diagnostic coverage and safety certification. Collaborates across hardware, software, design, verification, and external assessment teams to produce safety cases and achieve ISO 26262, IEC 61508, and related compliance.

Develops and validates manufacturing test content for FPGAs to detect defects, improve test coverage and yield, and optimize test time and cost. Responsibilities include DFT strategy, scan insertion, MBIST, ATPG, test pattern development, RTL integration, pre-silicon simulation, silicon failure analysis, customer return investigation, and collaboration with manufacturing and test teams.

Designs, integrates, validates, and debugs FPGA RTL systems for embedded, networking, SmartNIC, and acceleration applications. Responsibilities include integrating PCIe, Ethernet, EMIF, and ARM HPS IP; supporting board bring-up and system validation; developing software abstractions and drivers; collaborating on hardware/software co-development; optimizing performance; and contributing to FPGA-based product architecture, deployment, and customer investigations.

Designs, develops, and secures production-grade generative AI platforms, LLM, RAG, and agentic AI applications. Builds model-serving infrastructure, orchestration frameworks, observability and guardrails, and cloud-native services. Implements AI security, governance, threat modeling, vulnerability remediation, secure deployment, CI/CD, and DevSecOps practices across cloud and hybrid environments.