About Altera
At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
About the Role
As a Principal NoC IP Micro-Architect, you will be responsible for the end-to-end architecture, microarchitecture, RTL design, and technical leadership of scalable NoC IP solutions integrated into Altera's next-generation FPGA platforms. You will work closely with architecture, design, verification, software, physical design, and product teams to deliver high-performance interconnect solutions optimized for power, performance, area (PPA), scalability, and reliability.
This is a highly visible technical leadership role requiring deep expertise in SoC interconnect architectures, NoC fabrics, RTL development, performance modeling, and system-level optimization.
Key Responsibilities
Develops the logic design, register transfer level (RTL) coding, and simulation for Network on Chip IPs and potentially other FPGA IPs & subsystem for integration in full chip designs.
Participates in the definition of architecture and microarchitecture features of the block being designed.
Creates prototypes, simulates models, and specifies systems requirements.
Prepares and designs logic diagrams and codes for implementing system design and test specifications.
Delivers software models for device level bring up, including user visible functionality, timing, and power.
Applies RTL implementation techniques to qualify the design to meet required power, performance, and area goals, partnering with physical implementation team.
Strong understanding of the design methodology & advance EDA tools like timing constrains verification, RTL lint, CDC, RDC & DFT to ensure high quality IP development as well as deploying automation & AI to enhanced the development efficiency.
Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
As a senior designer of the team, you're also expected to groom next level technical members, technically oversee & guide the entire NOC team as well as proactively anticipate potential design challenges & roadblocks and take mitigation actions to ensure the successful execution of the SS that meets the requirement of the project & schedule.
Salary Range
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$209,500 - $299,200 USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
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Qualifications:Minimum Qualifications:
Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering, or a related field with 15+ years of related working experience.
10 + years of experience in System Verilog, VCS/Synopsys simulators, Lint and Synthesis
10+ years of experience in programming with C/C++/Perl/Python/TCL/Unix Shell script
10+ years of experience in FPGA design and programming is a plus.
10+ years of experience in RTL validation is a plus.
10+ years of experience in development of Network on Chip IPs.
5+ years of experience with the usage of AI with development process for high efficiency development would be a great plus.
Skills Required
- Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering, or related field with 15+ years experience
- 15+ years related working experience (overall)
- 10+ years experience in System Verilog
- 10+ years experience with VCS/Synopsys simulators
- 10+ years experience with lint and synthesis flows
- 10+ years programming experience in C/C++/Perl/Python/TCL/Unix Shell scripting
- 10+ years experience in development of Network on Chip IPs
- Experience with RTL validation
- Experience in FPGA design and programming
- Experience with EDA tools and methodologies: timing constraints verification, RTL lint, CDC, RDC, DFT
- Experience applying AI/automation to development processes
Altera (altera.com) Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Altera (altera.com) and has not been reviewed or approved by Altera (altera.com).
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Retirement Support — Feedback suggests retirement programs are robust, with offerings such as a 401(k) and a pension. This breadth supports long-term financial security.
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Leave & Time Off Breadth — Feedback suggests time-off policies are generous, including PTO, paid sick days, and paid holidays. Wellness initiatives like gym memberships further support balance.
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Parental & Family Support — Feedback suggests parental leave is generous. Family-building support, including fertility benefits and adoption reimbursement, is highlighted as part of the package.
Altera (altera.com) Insights
What We Do
Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.
