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As a Digital Verification Engineer Expert, you will validate digital products, propose verification strategies, mentor team members, and ensure project timelines are met.

The Product Line Manager will manage the product portfolio, develop strategies, define roadmaps, and collaborate with teams to commercialize technologies in interconnects. Responsibilities include customer assessment, feature gathering, and market analysis for coherent modem solutions.

The Director of Strategic Transactions will lead M&A, investments, and strategic partnerships, enhancing deal processes and legal frameworks in Ciena's Legal Department.

The Data Management Lead defines data strategy and architecture for telecom data, aligning it with AI and automation, while driving product innovation and implementing scalable solutions.

The role involves designing and integrating next-generation ASIC technologies, collaborating with engineers, and managing tool flows related to ASIC design and validation.

The Optical Components Product Engineer will oversee product design authority, collaborate with teams for production specifications, manage product lifecycle, and develop packaging for sustainability goals, requiring extensive experience in optoelectronic products.

The Manufacturing Test NPI Engineer will develop test automation solutions, validate test algorithms, and collaborate with teams for high-volume manufacturing of optical modules.

The engineer will develop automated tests, analyze data, and assist with product transitions, ensuring quality in optical products.

Support post-sales network solution engineering: translate designs into implementation plans, analyze customer network data, assist deployments, reconfigurations, and migrations, troubleshoot deployment package issues, and coordinate across engineering, field, and support teams under senior supervision.

Lead design and delivery of high-speed analog circuits in deep-submicron CMOS/BiCMOS for coherent optical systems, including optical-line ADCs, precision control/monitoring circuits, multi-phase clock generation, topology trade-offs, GDSII delivery, and lab characterization from test chips to full products.